From c0b2c10e9f3a939c227a26aec3ba377f7cc25667 Mon Sep 17 00:00:00 2001 From: Alexey Karyakin Date: Fri, 21 Mar 2025 20:08:45 -0500 Subject: [PATCH] [hexagon] Bump the default version to v68 (#132304) Set the default processor version to v68 when the user does not specify one in the command line. This includes changes in the LLVM backed and linker (lld). Since lld normally sets the version based on inputs, this change will only affect cases when there are no inputs. Fixes #127558 --- lld/ELF/Arch/Hexagon.cpp | 2 +- lld/docs/ReleaseNotes.rst | 5 ++ lld/test/ELF/emulation-hexagon.s | 4 +- lld/test/ELF/hexagon-eflag.s | 5 +- llvm/docs/ReleaseNotes.md | 4 ++ .../MCTargetDesc/HexagonMCTargetDesc.cpp | 2 +- llvm/test/CodeGen/Hexagon/arg-copy-elison.ll | 23 ++++---- .../Hexagon/atomicrmw-cond-sub-clamp.ll | 4 +- .../Hexagon/atomicrmw-uinc-udec-wrap.ll | 12 ++-- llvm/test/CodeGen/Hexagon/bank-conflict.mir | 2 +- .../Hexagon/branchfolder-insert-impdef.mir | 1 - .../CodeGen/Hexagon/fixed-spill-mutable.ll | 5 +- llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll | 56 ++++++++++--------- llvm/test/CodeGen/Hexagon/isel/logical.ll | 52 ++++++++--------- llvm/test/CodeGen/Hexagon/isel/select-i1.ll | 12 +--- .../CodeGen/Hexagon/postinc-baseoffset.mir | 4 +- llvm/test/CodeGen/Hexagon/setmemrefs.ll | 2 +- llvm/test/MC/Hexagon/arch-support.s | 4 ++ llvm/test/MC/Hexagon/hexagon_attributes.s | 12 ++-- ...agon_generated_funcs.ll.generated.expected | 33 ++++++----- ...on_generated_funcs.ll.nogenerated.expected | 33 ++++++----- 21 files changed, 145 insertions(+), 132 deletions(-) diff --git a/lld/ELF/Arch/Hexagon.cpp b/lld/ELF/Arch/Hexagon.cpp index 23b60672f631..4ba61db2733c 100644 --- a/lld/ELF/Arch/Hexagon.cpp +++ b/lld/ELF/Arch/Hexagon.cpp @@ -68,7 +68,7 @@ uint32_t Hexagon::calcEFlags() const { if (!ret || eflags > *ret) ret = eflags; } - return ret.value_or(/* Default Arch Rev: */ 0x60); + return ret.value_or(/* Default Arch Rev: */ EF_HEXAGON_MACH_V68); } static uint32_t applyMask(uint32_t mask, uint32_t data) { diff --git a/lld/docs/ReleaseNotes.rst b/lld/docs/ReleaseNotes.rst index 133a6fe87402..431b694f7bce 100644 --- a/lld/docs/ReleaseNotes.rst +++ b/lld/docs/ReleaseNotes.rst @@ -30,6 +30,11 @@ ELF Improvements from ``-zgcs-report`` (capped at ``warning`` level) unless user-defined, ensuring compatibility with GNU ld linker. +* The default Hexagon architecture version in ELF object files produced by + lld is changed to v68. This change is only effective when the version is + not provided in the command line by the user and cannot be inferred from + inputs. + Breaking changes ---------------- diff --git a/lld/test/ELF/emulation-hexagon.s b/lld/test/ELF/emulation-hexagon.s index a8a02d4c428b..5bdd88941c26 100644 --- a/lld/test/ELF/emulation-hexagon.s +++ b/lld/test/ELF/emulation-hexagon.s @@ -1,5 +1,5 @@ # REQUIRES: hexagon -# RUN: llvm-mc -filetype=obj -triple=hexagon %s -o %t.o +# RUN: llvm-mc -filetype=obj -triple=hexagon --mcpu=hexagonv73 %s -o %t.o # RUN: ld.lld %t.o -o %t # RUN: llvm-readelf --file-headers %t | FileCheck --check-prefix=CHECK %s # RUN: ld.lld -m hexagonelf %t.o -o %t @@ -26,7 +26,7 @@ # CHECK-NEXT: Entry point address: 0x200B4 # CHECK-NEXT: Start of program headers: 52 (bytes into file) # CHECK-NEXT: Start of section headers: -# CHECK-NEXT: Flags: 0x60 +# CHECK-NEXT: Flags: 0x73 # CHECK-NEXT: Size of this header: 52 (bytes) # CHECK-NEXT: Size of program headers: 32 (bytes) diff --git a/lld/test/ELF/hexagon-eflag.s b/lld/test/ELF/hexagon-eflag.s index dbe8604f69fd..ac9123832ac8 100644 --- a/lld/test/ELF/hexagon-eflag.s +++ b/lld/test/ELF/hexagon-eflag.s @@ -3,10 +3,11 @@ # RUN: llvm-mc -filetype=obj -mv60 -triple=hexagon-unknown-elf %S/Inputs/hexagon.s -o %t2 # RUN: ld.lld %t2 %t -o %t3 # RUN: llvm-readelf -h %t3 | FileCheck %s -# Verify that the largest arch in the input list is selected. +## Verify that the largest arch in the input list is selected. # CHECK: Flags: 0x62 +## Verify the arch version when it cannot be inferred from inputs. # RUN: llvm-ar rcsD %t4 # RUN: ld.lld -m hexagonelf %t4 -o %t5 # RUN: llvm-readelf -h %t5 | FileCheck --check-prefix=CHECK-EMPTYARCHIVE %s -# CHECK-EMPTYARCHIVE: Flags: 0x60 +# CHECK-EMPTYARCHIVE: Flags: 0x68 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 3b11cc3b0968..157065cb8621 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -104,6 +104,10 @@ Changes to the DirectX Backend Changes to the Hexagon Backend ------------------------------ +* The default Hexagon architecture version in ELF object files produced by + the tools such as llvm-mc is changed to v68. This version will be set if + the user does not provide the CPU version in the command line. + Changes to the LoongArch Backend -------------------------------- diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 4edbe4875c98..7f8315529e67 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -125,7 +125,7 @@ static cl::opt static cl::opt EnableHexagonCabac ("mcabac", cl::desc("tbd"), cl::init(false)); -static StringRef DefaultArch = "hexagonv60"; +static constexpr StringRef DefaultArch = "hexagonv68"; static StringRef HexagonGetArchVariant() { if (MV5) diff --git a/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll b/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll index f0c30c301f44..52f29eefa5ce 100644 --- a/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll +++ b/llvm/test/CodeGen/Hexagon/arg-copy-elison.ll @@ -1,8 +1,7 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs --version 4 ; RUN: llc -mtriple hexagon-- -o - %s | FileCheck %s ; Reproducer for https://github.com/llvm/llvm-project/issues/89060 -; ; Problem was a bug in argument copy elison. Given that the %alloca is ; eliminated, the same frame index will be used for accessing %alloca and %a ; on the fixed stack. Care must be taken when setting up @@ -11,8 +10,15 @@ ; ir.alloca name), or make sure that we still detect that they alias each ; other if using different kinds of MemOperands to identify the same fixed ; stack entry. -; define i32 @f(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %q1, i32 %a, i32 %q2) { + %alloca = alloca i32 + store i32 %a, ptr %alloca ; Should be elided. + store i32 666, ptr %alloca + %x = sub i32 %q1, %q2 + %y = xor i32 %x, %a ; Results in a load of %a from fixed stack. + ; Using same frame index as elided %alloca. + ret i32 %y +} ; CHECK-LABEL: f: ; CHECK: .cfi_startproc ; CHECK-NEXT: // %bb.0: @@ -24,16 +30,9 @@ define i32 @f(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i ; CHECK-NEXT: r0 = sub(r1,r0) ; CHECK-NEXT: r2 = memw(r29+#32) ; CHECK-NEXT: memw(r29+#32) = ##666 -; CHECK-NEXT: } +; CHECK-EMPTY: +; CHECK-NEXT: } :mem_noshuf ; CHECK-NEXT: { ; CHECK-NEXT: r0 = xor(r0,r2) ; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: } - %alloca = alloca i32 - store i32 %a, ptr %alloca ; Should be elided. - store i32 666, ptr %alloca - %x = sub i32 %q1, %q2 - %y = xor i32 %x, %a ; Results in a load of %a from fixed stack. - ; Using same frame index as elided %alloca. - ret i32 %y -} diff --git a/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll b/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll index ba09c3e2852d..0e0b64aac4f6 100644 --- a/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll +++ b/llvm/test/CodeGen/Hexagon/atomicrmw-cond-sub-clamp.ll @@ -152,10 +152,8 @@ define i64 @atomicrmw_usub_cond_i64(ptr %ptr, i64 %val) { ; CHECK-NEXT: r5:4 = memd_locked(r0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7:6 = sub(r5:4,r3:2) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4) +; CHECK-NEXT: r7:6 = sub(r5:4,r3:2) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r8 = mux(p0,r4,r6) diff --git a/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll index 6b6946d0dbb0..8e673c1bb06b 100644 --- a/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/Hexagon/atomicrmw-uinc-udec-wrap.ll @@ -156,12 +156,12 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; CHECK-NEXT: r5:4 = memd_locked(r0) ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4) ; CHECK-NEXT: r9:8 = add(r5:4,r7:6) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: p0 = cmp.gtu(r3:2,r5:4) -; CHECK-NEXT: if (!p0.new) r8 = add(r1,#0) -; CHECK-NEXT: if (!p0.new) r9 = add(r1,#0) +; CHECK-NEXT: if (!p0) r8 = add(r1,#0) +; CHECK-NEXT: if (!p0) r9 = add(r1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: memd_locked(r0,p0) = r9:8 @@ -345,13 +345,13 @@ define i64 @atomicrmw_udec_wrap_i64(ptr %ptr, i64 %val) { ; CHECK-NEXT: r5:4 = memd_locked(r0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r13:12 = add(r5:4,r7:6) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p1 = cmp.gtu(r5:4,r3:2) ; CHECK-NEXT: p0 = cmp.eq(r5:4,r9:8) ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: r13:12 = add(r5:4,r7:6) +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: r1 = mux(p1,r2,r12) ; CHECK-NEXT: r14 = mux(p1,r3,r13) ; CHECK-NEXT: } diff --git a/llvm/test/CodeGen/Hexagon/bank-conflict.mir b/llvm/test/CodeGen/Hexagon/bank-conflict.mir index 0add375786c3..1f5edef6576d 100644 --- a/llvm/test/CodeGen/Hexagon/bank-conflict.mir +++ b/llvm/test/CodeGen/Hexagon/bank-conflict.mir @@ -9,9 +9,9 @@ # CHECK: = A2_tfr # CHECK: = L2_loadrigp -# CHECK: = L4_loadri_rr # CHECK: = S2_tstbit_i # CHECK: = L4_loadri_rr +# CHECK: = L4_loadri_rr --- | %s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] } diff --git a/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir b/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir index 5e8043247175..97f57fcc97e9 100644 --- a/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir +++ b/llvm/test/CodeGen/Hexagon/branchfolder-insert-impdef.mir @@ -1,5 +1,4 @@ # RUN: llc -mtriple=hexagon -run-pass branch-folder %s -o - -verify-machineinstrs | FileCheck %s -# RUN: llc -mtriple=hexagon -passes="require,function(machine-function(branch-folder))" %s -o - -verify-machineinstrs | FileCheck %s # Branch folding will perform tail merging of bb.1 and bb.2, and bb.2 will # become the common tail. The use of R0 in bb.2 is while the diff --git a/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll b/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll index f99b448cc1a7..aa8766661a24 100644 --- a/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll +++ b/llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll @@ -12,10 +12,11 @@ ; The problem is that the load will execute before the store, clobbering the ; pair r17:16. ; -; Check that the store and the load are not in the same packet. + +; Validate that store executes before load. ; CHECK: memd{{.*}} = r17:16 -; CHECK: } ; CHECK: r17:16 = memd +; CHECK: } :mem_noshuf ; CHECK-LABEL: LBB0_1: target triple = "hexagon" diff --git a/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll b/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll index e1b848c0d247..23c919df0555 100644 --- a/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll +++ b/llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll @@ -8,12 +8,15 @@ define i64 @f0(ptr %a0, <8 x i8> %a1) #0 { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5:4 = combine(#0,#0) +; CHECK-NEXT: r1 = #0 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = r0 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: r5:4 = vsplatb(r1) +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: r1:0 = vmux(p0,r3:2,r5:4) ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -114,7 +117,10 @@ define void @f4(ptr %a0, i64 %a1) #0 { ; CHECK-LABEL: f4: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r5:4 = combine(#0,#0) +; CHECK-NEXT: r1 = #0 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r5:4 = vsplatb(r1) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r3:2,r5:4) @@ -123,10 +129,10 @@ define void @f4(ptr %a0, i64 %a1) #0 { ; CHECK-NEXT: p0 = not(p0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r1 = p0 +; CHECK-NEXT: r2 = p0 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: memb(r0+#0) = r1 +; CHECK-NEXT: memb(r0+#0) = r2 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 @@ -173,64 +179,64 @@ define void @f6(ptr %a0, i16 %a1) #0 { ; CHECK-LABEL: f6: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r2 = extractu(r1,#8,#8) +; CHECK-NEXT: r2 = #255 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r3 = #255 +; CHECK-NEXT: r3 = extractu(r1,#8,#8) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: p1 = !bitsclr(r1,r3) +; CHECK-NEXT: p1 = !bitsclr(r1,r2) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: p0 = cmp.eq(r2,#0) +; CHECK-NEXT: p0 = cmp.eq(r3,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (p0) r2 = #0 +; CHECK-NEXT: if (p0) r3 = #0 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r1 = mux(p1,#8,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r3 = mux(p1,#2,#0) +; CHECK-NEXT: r2 = mux(p1,#2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = setbit(r1,#2) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: r6 = setbit(r3,#0) -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: if (!p0) r2 = #128 +; CHECK-NEXT: if (!p0) r3 = #128 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: r4 = mux(p0,#0,#32) ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: r5 = setbit(r1,#2) +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: r6 = setbit(r2,#0) +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: if (!p1) r5 = add(r1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p1) r6 = add(r3,#0) +; CHECK-NEXT: r1 = setbit(r3,#6) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r1 = setbit(r2,#6) +; CHECK-NEXT: if (!p1) r6 = add(r2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r3 = setbit(r4,#4) +; CHECK-NEXT: r2 = setbit(r4,#4) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = or(r6,r5) +; CHECK-NEXT: if (!p0) r4 = add(r2,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p0) r2 = add(r1,#0) +; CHECK-NEXT: if (!p0) r3 = add(r1,#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: if (!p0) r4 = add(r3,#0) +; CHECK-NEXT: r2 = or(r6,r5) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 |= or(r4,r2) +; CHECK-NEXT: r2 |= or(r4,r3) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: memb(r0+#0) = r5 +; CHECK-NEXT: memb(r0+#0) = r2 ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: jumpr r31 diff --git a/llvm/test/CodeGen/Hexagon/isel/logical.ll b/llvm/test/CodeGen/Hexagon/isel/logical.ll index 7f9c178c4241..669d01dcd6ad 100644 --- a/llvm/test/CodeGen/Hexagon/isel/logical.ll +++ b/llvm/test/CodeGen/Hexagon/isel/logical.ll @@ -1399,10 +1399,10 @@ define <8 x i8> @f39(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f39: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1431,10 +1431,10 @@ define <8 x i8> @f40(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f40: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1463,10 +1463,10 @@ define <8 x i8> @f41(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f41: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1495,10 +1495,10 @@ define <8 x i8> @f42(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f42: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1528,10 +1528,10 @@ define <8 x i8> @f43(<8 x i8> %a0, <8 x i8> %a1) #1 { ; CHECK-LABEL: f43: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r4 = ##16843009 +; CHECK-NEXT: r4 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r5 = ##16843009 +; CHECK-NEXT: r5:4 = vsplatb(r4) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r5:4) @@ -1561,10 +1561,10 @@ define <8 x i8> @f44(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f44: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1598,10 +1598,10 @@ define <8 x i8> @f45(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f45: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1635,10 +1635,10 @@ define <8 x i8> @f46(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f46: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1672,10 +1672,10 @@ define <8 x i8> @f47(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f47: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1709,10 +1709,10 @@ define <8 x i8> @f48(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f48: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1750,10 +1750,10 @@ define <8 x i8> @f49(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f49: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1788,10 +1788,10 @@ define <8 x i8> @f50(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f50: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) @@ -1826,10 +1826,10 @@ define <8 x i8> @f51(<8 x i8> %a0, <8 x i8> %a1, <8 x i8> %a2) #1 { ; CHECK-LABEL: f51: ; CHECK: // %bb.0: // %b0 ; CHECK-NEXT: { -; CHECK-NEXT: r6 = ##16843009 +; CHECK-NEXT: r6 = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r7 = ##16843009 +; CHECK-NEXT: r7:6 = vsplatb(r6) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p0 = vcmpb.eq(r1:0,r7:6) diff --git a/llvm/test/CodeGen/Hexagon/isel/select-i1.ll b/llvm/test/CodeGen/Hexagon/isel/select-i1.ll index 193b354bc5a8..eb77850f0a5a 100644 --- a/llvm/test/CodeGen/Hexagon/isel/select-i1.ll +++ b/llvm/test/CodeGen/Hexagon/isel/select-i1.ll @@ -124,11 +124,9 @@ define void @f4(ptr %a0, ptr %a1, ptr %a2, ptr %a3) { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r2 = memub(r2+#0) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p0 = r0 ; CHECK-NEXT: p1 = r1 +; CHECK-NEXT: r2 = memub(r2+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p2 = r2 @@ -160,11 +158,9 @@ define void @f5(ptr %a0, ptr %a1, ptr %a2, ptr %a3) { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r2 = memub(r2+#0) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p0 = r0 ; CHECK-NEXT: p1 = r1 +; CHECK-NEXT: r2 = memub(r2+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p2 = r2 @@ -196,11 +192,9 @@ define void @f6(ptr %a0, ptr %a1, ptr %a2, ptr %a3) { ; CHECK-NEXT: r0 = memub(r0+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { -; CHECK-NEXT: r2 = memub(r2+#0) -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: p0 = r0 ; CHECK-NEXT: p1 = r1 +; CHECK-NEXT: r2 = memub(r2+#0) ; CHECK-NEXT: } ; CHECK-NEXT: { ; CHECK-NEXT: p2 = r2 diff --git a/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir b/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir index fa07febcbf5a..172a28b8e64e 100644 --- a/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir +++ b/llvm/test/CodeGen/Hexagon/postinc-baseoffset.mir @@ -2,11 +2,11 @@ # Check that we don't packetize these two instructions together. It happened # earlier because "offset" in the post-increment instruction was taken to be 8. +# If they are packetized together, make sure "mem_noshuf" attribute is set. # CHECK: memw(r0+#0) = #-1 -# CHECK: } -# CHECK: { # CHECK: r1 = memw(r0++#8) +# CHECK: :mem_noshuf --- | define void @fred(ptr %a) { ret void } diff --git a/llvm/test/CodeGen/Hexagon/setmemrefs.ll b/llvm/test/CodeGen/Hexagon/setmemrefs.ll index 85f46af7e56a..13b7b955cb62 100644 --- a/llvm/test/CodeGen/Hexagon/setmemrefs.ll +++ b/llvm/test/CodeGen/Hexagon/setmemrefs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=hexagon < %s | FileCheck %s +; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 < %s | FileCheck %s ; This test checks to see if, after lowering the two loads below, we set up the ; memrefs of the resulting load MIs correctly, so that they are packetized diff --git a/llvm/test/MC/Hexagon/arch-support.s b/llvm/test/MC/Hexagon/arch-support.s index 99364cc93691..eb362a7db3ca 100644 --- a/llvm/test/MC/Hexagon/arch-support.s +++ b/llvm/test/MC/Hexagon/arch-support.s @@ -11,6 +11,9 @@ # RUN: llvm-mc -triple=hexagon -mv75 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V75 %s # RUN: llvm-mc -triple=hexagon -mv79 -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-V79 %s +## Check which arch version llvm-mc sets when the user does not provide one. +# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-readelf -h - | FileCheck --check-prefix=CHECK-DEFAULT %s + # RUN: llvm-mc -triple=hexagon -mv5 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s # RUN: llvm-mc -triple=hexagon -mv55 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s # RUN: llvm-mc -triple=hexagon -mv60 -filetype=obj %s | llvm-objdump --disassemble - | FileCheck --check-prefix=CHECK-OBJDUMP %s @@ -38,5 +41,6 @@ r1 = r1 # CHECK-V73: Flags:{{.*}}0x73 # CHECK-V75: Flags:{{.*}}0x75 # CHECK-V79: Flags:{{.*}}0x79 +# CHECK-DEFAULT: Flags:{{.*}}0x68 # CHECK-OBJDUMP: { r1 = r1 } diff --git a/llvm/test/MC/Hexagon/hexagon_attributes.s b/llvm/test/MC/Hexagon/hexagon_attributes.s index 4cd5223cd220..8d96993eee99 100644 --- a/llvm/test/MC/Hexagon/hexagon_attributes.s +++ b/llvm/test/MC/Hexagon/hexagon_attributes.s @@ -5,8 +5,11 @@ r3:2=cround(r1:0,#0x0) // v67, audio v3:0.w=vrmpyz(v0.b,r0.b) // hvxv73, zreg v1:0.sf=vadd(v0.bf,v0.bf) // hvxv73, hvx-ieee-fp -// RUN: llvm-mc --mattr=+v67,+hvxv73,+hvx-qfloat,+hvx-ieee-fp,+zreg,+audio %s \ -// RUN: -triple=hexagon -filetype=obj --hexagon-add-build-attributes -o %t.o +// Note that the CPU version should be set with `--mcpu` and not with attributes +// because attributes are additive. +// RUN: llvm-mc -triple=hexagon --mcpu=hexagonv67 \ +// RUN: --mattr=+hvxv73,+hvx-qfloat,+hvx-ieee-fp,+zreg,+audio %s \ +// RUN: -filetype=obj --hexagon-add-build-attributes -o %t.o // RUN: llvm-readelf -A %t.o | \ // RUN: FileCheck %s --match-full-lines --implicit-check-not={{.}} --check-prefix=READELF @@ -15,8 +18,9 @@ v1:0.sf=vadd(v0.bf,v0.bf) // hvxv73, hvx-ieee-fp /// without manually passing in features when an attribute section is present. // RUN: llvm-objdump -d %t.o | FileCheck %s --check-prefix=OBJDUMP -// RUN: llvm-mc --mattr=+v67,+hvxv73,+hvx-qfloat,+hvx-ieee-fp,+zreg,+audio %s \ -// RUN: -triple=hexagon -filetype=asm --hexagon-add-build-attributes | \ +// RUN: llvm-mc -triple=hexagon --mcpu=hexagonv67 \ +// RUN: --mattr=+hvxv73,+hvx-qfloat,+hvx-ieee-fp,+zreg,+audio %s \ +// RUN: -filetype=asm --hexagon-add-build-attributes | \ // RUN: FileCheck %s --match-full-lines --implicit-check-not={{.}} --check-prefix=ASM // READELF: BuildAttributes { diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected index cd135ce9e011..e54510ba8e04 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.generated.expected @@ -76,29 +76,28 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .cfi_offset r30, -8 ; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#4) = #0 -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#8) = #0 +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#8) = #1 -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: r1 = memw(r29+#8) -; CHECK-NEXT: memw(r29+#12) = #2 -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: memw(r29+#16) = #3 -; CHECK-NEXT: memw(r29+#20) = #4 -; CHECK-NEXT: } +; CHECK-EMPTY: +; CHECK-NEXT: } :mem_noshuf ; CHECK-NEXT: { ; CHECK-NEXT: p0 = cmp.eq(r1,#0) -; CHECK-NEXT: if (p0.new) memw(r29+#16) = #3 -; CHECK-NEXT: if (p0.new) memw(r29+#12) = #2 +; CHECK-NEXT: memw(r29+#12) = #2 +; CHECK-NEXT: memw(r29+#16) = #3 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: memw(r29+#20) = #4 +; CHECK-NEXT: if (p0) memw(r29+#16) = #3 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if (p0) memw(r29+#12) = #2 ; CHECK-NEXT: if (p0) memw(r29+#20) = #4 -; CHECK-NEXT: if (p0) memw(r29+#8) = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: if (p0) memw(r29+#8) = #1 ; CHECK-NEXT: if (!p0) memw(r29+#16) = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -117,15 +116,15 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: .cfi_offset r30, -8 ; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#4) = #0 -; CHECK-NEXT: memw(r0+#0) = #1 -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#8) = #1 -; CHECK-NEXT: memw(r29+#12) = #2 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: memw(r29+#12) = #2 ; CHECK-NEXT: memw(r29+#16) = #3 +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#20) = #4 +; CHECK-NEXT: memw(r0+#0) = #1 ; CHECK-NEXT: } ; CHECK-NEXT: //# InlineAsm Start ; CHECK-NEXT: //# InlineAsm End diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected index 833bf68fc03d..219d6d004fd8 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/hexagon_generated_funcs.ll.nogenerated.expected @@ -17,29 +17,28 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: .cfi_offset r30, -8 ; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#4) = #0 -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#8) = #0 +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#8) = #1 -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: r1 = memw(r29+#8) -; CHECK-NEXT: memw(r29+#12) = #2 -; CHECK-NEXT: } -; CHECK-NEXT: { -; CHECK-NEXT: memw(r29+#16) = #3 -; CHECK-NEXT: memw(r29+#20) = #4 -; CHECK-NEXT: } +; CHECK-EMPTY: +; CHECK-NEXT: } :mem_noshuf ; CHECK-NEXT: { ; CHECK-NEXT: p0 = cmp.eq(r1,#0) -; CHECK-NEXT: if (p0.new) memw(r29+#16) = #3 -; CHECK-NEXT: if (p0.new) memw(r29+#12) = #2 +; CHECK-NEXT: memw(r29+#12) = #2 +; CHECK-NEXT: memw(r29+#16) = #3 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: memw(r29+#20) = #4 +; CHECK-NEXT: if (p0) memw(r29+#16) = #3 +; CHECK-NEXT: } +; CHECK-NEXT: { +; CHECK-NEXT: if (p0) memw(r29+#12) = #2 ; CHECK-NEXT: if (p0) memw(r29+#20) = #4 -; CHECK-NEXT: if (p0) memw(r29+#8) = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: if (p0) memw(r29+#8) = #1 ; CHECK-NEXT: if (!p0) memw(r29+#16) = #1 ; CHECK-NEXT: } ; CHECK-NEXT: { @@ -94,15 +93,15 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: .cfi_offset r30, -8 ; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#4) = #0 -; CHECK-NEXT: memw(r0+#0) = #1 -; CHECK-NEXT: } -; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#8) = #1 -; CHECK-NEXT: memw(r29+#12) = #2 ; CHECK-NEXT: } ; CHECK-NEXT: { +; CHECK-NEXT: memw(r29+#12) = #2 ; CHECK-NEXT: memw(r29+#16) = #3 +; CHECK-NEXT: } +; CHECK-NEXT: { ; CHECK-NEXT: memw(r29+#20) = #4 +; CHECK-NEXT: memw(r0+#0) = #1 ; CHECK-NEXT: } ; CHECK-NEXT: //# InlineAsm Start ; CHECK-NEXT: //# InlineAsm End