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[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)

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Rename RISCV32GPRPair and RISCV32Only_ to RV32Only. This gives a more
natural home for the P extension RV32 conflicts.

While I was there I made some improvements to the debug messages.
This commit is contained in:
Craig Topper 2025-03-17 12:49:08 -07:00 committed by GitHub
parent 9eb6b37e39
commit d2e1e30348
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GPG Key ID: B5690EEEBB952194
4 changed files with 15 additions and 17 deletions
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18
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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@ -690,12 +690,10 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
{DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
{DecoderTable32, {}, "RISCV32"},
{DecoderTableRV32GPRPair32, {}, "RV32GPRPair (rv32 and GPR pairs)"},
{DecoderTable32, {}, "standard 32-bit instructions"},
{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
{DecoderTableZdinxRV32GPRPair32,
{},
"ZdinxRV32GPRPair (rv32 and Double in Integer)"},
{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
};
DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
@ -714,7 +712,7 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
continue;
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << "table:\n");
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
DecodeStatus Result =
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
if (Result == MCDisassembler::Fail)
@ -728,16 +726,16 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
static constexpr DecoderListEntry DecoderList16[]{
// Vendor Extensions
{DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16bit"},
{DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
{DecoderTableXqccmp16,
{RISCV::FeatureVendorXqccmp},
"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
{DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
// Standard Extensions
// DecoderTableZicfiss16 must be checked before DecoderTable16.
{DecoderTableZicfiss16, {}, "RVZicfiss (Shadow Stack)"},
{DecoderTable16, {}, "RISCV_C (16-bit Instruction)"},
{DecoderTableRISCV32Only_16, {}, "RISCV32Only_16 (16-bit Instruction)"},
{DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
{DecoderTable16, {}, "standard 16-bit instructions"},
{DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
// Zc* instructions incompatible with Zcf or Zcd
{DecoderTableZcOverlap16,
{},

10
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
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@ -332,7 +332,7 @@ def C_LW_INX : CLoad_ri<0b010, "c.lw", GPRF32C, uimm7_lsb00>,
let Inst{5} = imm{6};
}
let DecoderNamespace = "RISCV32Only_",
let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FLW : CLoad_ri<0b011, "c.flw", FPR32C, uimm7_lsb00>,
Sched<[WriteFLD32, ReadFMemBase]> {
@ -375,7 +375,7 @@ def C_SW_INX : CStore_rri<0b110, "c.sw", GPRF32C, uimm7_lsb00>,
let Inst{5} = imm{6};
}
let DecoderNamespace = "RISCV32Only_",
let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSW : CStore_rri<0b111, "c.fsw", FPR32C, uimm7_lsb00>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {
@ -415,7 +415,7 @@ def PseudoC_ADDI_NOP : Pseudo<(outs GPRX0:$rd), (ins GPRX0:$rs1, immzero:$imm),
[], "c.addi", "$rd, $imm">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1,
DecoderNamespace = "RISCV32Only_", Defs = [X1],
DecoderNamespace = "RV32Only", Defs = [X1],
Predicates = [HasStdExtCOrZca, IsRV32] in
def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
"c.jal", "$offset">, Sched<[WriteJal]>;
@ -521,7 +521,7 @@ def C_LWSP_INX : CStackLoad<0b010, "c.lwsp", GPRF32NoX0, uimm8_lsb00>,
let Inst{3-2} = imm{7-6};
}
let DecoderNamespace = "RISCV32Only_",
let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FLWSP : CStackLoad<0b011, "c.flwsp", FPR32, uimm8_lsb00>,
Sched<[WriteFLD32, ReadFMemBase]> {
@ -581,7 +581,7 @@ def C_SWSP_INX : CStackStore<0b110, "c.swsp", GPRF32, uimm8_lsb00>,
let Inst{8-7} = imm{7-6};
}
let DecoderNamespace = "RISCV32Only_",
let DecoderNamespace = "RV32Only",
Predicates = [HasStdExtCOrZcfOrZce, HasStdExtF, IsRV32] in
def C_FSWSP : CStackStore<0b111, "c.fswsp", FPR32, uimm8_lsb00>,
Sched<[WriteFST32, ReadFStoreData, ReadFMemBase]> {

2
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
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@ -62,7 +62,7 @@ def DExt : ExtInfo<"", "", [HasStdExtD], f64, FPR64, FPR32, FPR64, ?>;
def ZdinxExt : ExtInfo<"_INX", "Zfinx", [HasStdExtZdinx, IsRV64],
f64, FPR64INX, FPR32INX, FPR64INX, ?>;
def Zdinx32Ext : ExtInfo<"_IN32X", "ZdinxRV32GPRPair", [HasStdExtZdinx, IsRV32],
def Zdinx32Ext : ExtInfo<"_IN32X", "ZdinxRV32Only", [HasStdExtZdinx, IsRV32],
f64, FPR64IN32X, FPR32INX, FPR64IN32X, ?>;
defvar DExts = [DExt, ZdinxExt, Zdinx32Ext];

2
llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
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@ -59,7 +59,7 @@ let Predicates = [HasStdExtZacas], IsSignExtendingOpW = 1 in {
defm AMOCAS_W : AMO_cas_aq_rl<0b00101, 0b010, "amocas.w", GPR>;
} // Predicates = [HasStdExtZacas]
let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32GPRPair" in {
let Predicates = [HasStdExtZacas, IsRV32], DecoderNamespace = "RV32Only" in {
defm AMOCAS_D_RV32 : AMO_cas_aq_rl<0b00101, 0b011, "amocas.d", GPRPairRV32>;
} // Predicates = [HasStdExtZacas, IsRV32]