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[RISCV] Add Syntacore SCR7 processor definition (#108406)

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Syntacore SCR7 is a high-performance Linux-capable RISC-V processor
core.
The core has rv64imafdcv_zba_zbb_zbc_zbs_zkn march.
Overview: https://syntacore.com/products/scr7

Scheduling model will be added in a subsequent PR.

---------

Co-authored-by: Dmitrii Petrov <dmitrii.petrov@syntacore.com>
Co-authored-by: Anton Afanasyev <anton.afanasyev@syntacore.com>
Co-authored-by: Elena Lepilkina <elena.lepilkina@syntacore.com>
This commit is contained in:
Anton Sidorenko 2024-09-16 13:09:37 +03:00 committed by GitHub
parent feac761f37
commit dbdf84388a
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26
clang/test/Driver/riscv-cpus.c
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@ -502,3 +502,29 @@
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr5-rv64 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR5-RV64 %s
// MTUNE-SYNTACORE-SCR5-RV64: "-tune-cpu" "syntacore-scr5-rv64"
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=syntacore-scr7 | FileCheck -check-prefix=MCPU-SYNTACORE-SCR7 %s
// MCPU-SYNTACORE-SCR7: "-target-cpu" "syntacore-scr7"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+m"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+a"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+f"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+d"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+c"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+v"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zicsr"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zifencei"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zba"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbb"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbc"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkb"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkc"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbkx"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zbs"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkn"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknd"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zkne"
// MCPU-SYNTACORE-SCR7-SAME: "-target-feature" "+zknh"
// MCPU-SYNTACORE-SCR7-SAME: "-target-abi" "lp64d"
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"

2
clang/test/Misc/target-invalid-cpu-note/riscv.c
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@ -40,6 +40,7 @@
// RISCV64-SAME: {{^}}, syntacore-scr3-rv64
// RISCV64-SAME: {{^}}, syntacore-scr4-rv64
// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// RISCV64-SAME: {{^}}, syntacore-scr7
// RISCV64-SAME: {{^}}, veyron-v1
// RISCV64-SAME: {{^}}, xiangshan-nanhu
// RISCV64-SAME: {{$}}
@ -85,6 +86,7 @@
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, generic

1
llvm/docs/ReleaseNotes.rst
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@ -123,6 +123,7 @@ Changes to the RISC-V Backend
largely untested.
* The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
* Added ``Smctr`` and ``Ssctr`` extensions.
* ``-mcpu=syntacore-scr7`` was added.
Changes to the WebAssembly Backend
----------------------------------

19
llvm/lib/Target/RISCV/RISCVProcessors.td
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@ -383,6 +383,25 @@ def SYNTACORE_SCR5_RV64 : RISCVProcessorModel<"syntacore-scr5-rv64",
FeatureStdExtC],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
NoSchedModel,
[Feature64Bit,
FeatureStdExtI,
FeatureStdExtZicsr,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtV,
FeatureStdExtZba,
FeatureStdExtZbb,
FeatureStdExtZbc,
FeatureStdExtZbs,
FeatureStdExtZkn],
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
NoSchedModel,
[Feature64Bit,