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[AArch64] Add @llvm.experimental.vector.match (#101974)
This patch introduces an experimental intrinsic for matching the elements of one vector against the elements of another. For AArch64 targets that support SVE2, the intrinsic lowers to a MATCH instruction for supported fixed and scalar vector types.
This commit is contained in:
Ricardo Jesus
GitHub
parent
debfd7b0b4
commit
e52238b59f
@ -20091,6 +20091,44 @@ are undefined.
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}
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'``llvm.experimental.vector.match.*``' Intrinsic
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Syntax:
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"""""""
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This is an overloaded intrinsic.
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::
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declare <<n> x i1> @llvm.experimental.vector.match(<<n> x <ty>> %op1, <<m> x <ty>> %op2, <<n> x i1> %mask)
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declare <vscale x <n> x i1> @llvm.experimental.vector.match(<vscale x <n> x <ty>> %op1, <<m> x <ty>> %op2, <vscale x <n> x i1> %mask)
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Overview:
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"""""""""
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Find active elements of the first argument matching any elements of the second.
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Arguments:
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""""""""""
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The first argument is the search vector, the second argument the vector of
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elements we are searching for (i.e. for which we consider a match successful),
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and the third argument is a mask that controls which elements of the first
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argument are active. The first two arguments must be vectors of matching
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integer element types. The first and third arguments and the result type must
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have matching element counts (fixed or scalable). The second argument must be a
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fixed vector, but its length may be different from the remaining arguments.
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Semantics:
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""""""""""
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The '``llvm.experimental.vector.match``' intrinsic compares each active element
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in the first argument against the elements of the second argument, placing
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``1`` in the corresponding element of the output vector if any equality
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comparison is successful, and ``0`` otherwise. Inactive elements in the mask
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are set to ``0`` in the output.
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Matrix Intrinsics
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-----------------
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@ -483,6 +483,13 @@ public:
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bool ZeroIsPoison,
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const ConstantRange *VScaleRange) const;
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/// Return true if the @llvm.experimental.vector.match intrinsic should be
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/// expanded for vector type `VT' and search size `SearchSize' using generic
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/// code in SelectionDAGBuilder.
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virtual bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const {
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return true;
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}
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// Return true if op(vecreduce(x), vecreduce(y)) should be reassociated to
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// vecreduce(op(x, y)) for the reduction opcode RedOpc.
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virtual bool shouldReassociateReduction(unsigned RedOpc, EVT VT) const {
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@ -1920,6 +1920,14 @@ def int_experimental_vector_histogram_add : DefaultAttrsIntrinsic<[],
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], // Mask
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[ IntrArgMemOnly ]>;
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// Experimental match
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def int_experimental_vector_match : DefaultAttrsIntrinsic<
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[ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ],
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[ llvm_anyvector_ty,
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llvm_anyvector_ty,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty> ], // Mask
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[ IntrNoMem, IntrNoSync, IntrWillReturn ]>;
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// Operators
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let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in {
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// Integer arithmetic
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@ -8175,6 +8175,36 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index));
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return;
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}
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case Intrinsic::experimental_vector_match: {
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SDValue Op1 = getValue(I.getOperand(0));
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SDValue Op2 = getValue(I.getOperand(1));
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SDValue Mask = getValue(I.getOperand(2));
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EVT Op1VT = Op1.getValueType();
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EVT Op2VT = Op2.getValueType();
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EVT ResVT = Mask.getValueType();
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unsigned SearchSize = Op2VT.getVectorNumElements();
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// If the target has native support for this vector match operation, lower
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// the intrinsic untouched; otherwise, expand it below.
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if (!TLI.shouldExpandVectorMatch(Op1VT, SearchSize)) {
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visitTargetIntrinsic(I, Intrinsic);
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return;
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}
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SDValue Ret = DAG.getConstant(0, sdl, ResVT);
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for (unsigned i = 0; i < SearchSize; ++i) {
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SDValue Op2Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
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Op2VT.getVectorElementType(), Op2,
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DAG.getVectorIdxConstant(i, sdl));
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SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, sdl, Op1VT, Op2Elem);
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SDValue Cmp = DAG.getSetCC(sdl, ResVT, Op1, Splat, ISD::SETEQ);
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Ret = DAG.getNode(ISD::OR, sdl, ResVT, Ret, Cmp);
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}
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setValue(&I, DAG.getNode(ISD::AND, sdl, ResVT, Ret, Mask));
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return;
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}
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case Intrinsic::vector_reverse:
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visitVectorReverse(I);
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return;
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@ -6150,6 +6150,31 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) {
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&Call);
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break;
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}
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case Intrinsic::experimental_vector_match: {
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Value *Op1 = Call.getArgOperand(0);
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Value *Op2 = Call.getArgOperand(1);
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Value *Mask = Call.getArgOperand(2);
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VectorType *Op1Ty = dyn_cast<VectorType>(Op1->getType());
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VectorType *Op2Ty = dyn_cast<VectorType>(Op2->getType());
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VectorType *MaskTy = dyn_cast<VectorType>(Mask->getType());
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Check(Op1Ty && Op2Ty && MaskTy, "Operands must be vectors.", &Call);
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Check(isa<FixedVectorType>(Op2Ty),
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"Second operand must be a fixed length vector.", &Call);
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Check(Op1Ty->getElementType()->isIntegerTy(),
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"First operand must be a vector of integers.", &Call);
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Check(Op1Ty->getElementType() == Op2Ty->getElementType(),
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"First two operands must have the same element type.", &Call);
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Check(Op1Ty->getElementCount() == MaskTy->getElementCount(),
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"First operand and mask must have the same number of elements.",
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&Call);
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Check(MaskTy->getElementType()->isIntegerTy(1),
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"Mask must be a vector of i1's.", &Call);
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Check(Call.getType() == MaskTy, "Return type must match the mask type.",
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&Call);
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break;
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}
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case Intrinsic::vector_insert: {
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Value *Vec = Call.getArgOperand(0);
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Value *SubVec = Call.getArgOperand(1);
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@ -2059,6 +2059,19 @@ bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const {
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VT != MVT::v4i1 && VT != MVT::v2i1;
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}
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bool AArch64TargetLowering::shouldExpandVectorMatch(EVT VT,
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unsigned SearchSize) const {
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// MATCH is SVE2 and only available in non-streaming mode.
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if (!Subtarget->hasSVE2() || !Subtarget->isSVEAvailable())
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return true;
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// Furthermore, we can only use it for 8-bit or 16-bit elements.
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if (VT == MVT::nxv8i16 || VT == MVT::v8i16)
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return SearchSize != 8;
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if (VT == MVT::nxv16i8 || VT == MVT::v16i8 || VT == MVT::v8i8)
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return SearchSize != 8 && SearchSize != 16;
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return true;
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}
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void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) {
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assert(VT.isFixedLengthVector() && "Expected fixed length vector type!");
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@ -5780,6 +5793,72 @@ SDValue LowerSMELdrStr(SDValue N, SelectionDAG &DAG, bool IsLoad) {
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DAG.getTargetConstant(ImmAddend, DL, MVT::i32)});
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}
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SDValue LowerVectorMatch(SDValue Op, SelectionDAG &DAG) {
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SDLoc dl(Op);
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SDValue ID =
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DAG.getTargetConstant(Intrinsic::aarch64_sve_match, dl, MVT::i64);
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auto Op1 = Op.getOperand(1);
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auto Op2 = Op.getOperand(2);
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auto Mask = Op.getOperand(3);
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EVT Op1VT = Op1.getValueType();
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EVT Op2VT = Op2.getValueType();
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EVT ResVT = Op.getValueType();
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assert((Op1VT.getVectorElementType() == MVT::i8 ||
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Op1VT.getVectorElementType() == MVT::i16) &&
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"Expected 8-bit or 16-bit characters.");
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// Scalable vector type used to wrap operands.
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// A single container is enough for both operands because ultimately the
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// operands will have to be wrapped to the same type (nxv16i8 or nxv8i16).
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EVT OpContainerVT = Op1VT.isScalableVector()
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? Op1VT
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: getContainerForFixedLengthVector(DAG, Op1VT);
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if (Op2VT.is128BitVector()) {
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// If Op2 is a full 128-bit vector, wrap it trivially in a scalable vector.
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Op2 = convertToScalableVector(DAG, OpContainerVT, Op2);
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// Further, if the result is scalable, broadcast Op2 to a full SVE register.
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if (ResVT.isScalableVector())
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Op2 = DAG.getNode(AArch64ISD::DUPLANE128, dl, OpContainerVT, Op2,
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DAG.getTargetConstant(0, dl, MVT::i64));
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} else {
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// If Op2 is not a full 128-bit vector, we always need to broadcast it.
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unsigned Op2BitWidth = Op2VT.getFixedSizeInBits();
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MVT Op2IntVT = MVT::getIntegerVT(Op2BitWidth);
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EVT Op2PromotedVT = getPackedSVEVectorVT(Op2IntVT);
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Op2 = DAG.getBitcast(MVT::getVectorVT(Op2IntVT, 1), Op2);
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Op2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op2IntVT, Op2,
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DAG.getConstant(0, dl, MVT::i64));
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Op2 = DAG.getSplatVector(Op2PromotedVT, dl, Op2);
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Op2 = DAG.getBitcast(OpContainerVT, Op2);
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}
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// If the result is scalable, we just need to carry out the MATCH.
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if (ResVT.isScalableVector())
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResVT, ID, Mask, Op1, Op2);
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// If the result is fixed, we can still use MATCH but we need to wrap the
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// first operand and the mask in scalable vectors before doing so.
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// Wrap the operands.
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Op1 = convertToScalableVector(DAG, OpContainerVT, Op1);
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Mask = DAG.getNode(ISD::SIGN_EXTEND, dl, Op1VT, Mask);
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Mask = convertFixedMaskToScalableVector(Mask, DAG);
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// Carry out the match.
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SDValue Match = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, Mask.getValueType(),
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ID, Mask, Op1, Op2);
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// Extract and promote the match result (nxv16i1/nxv8i1) to ResVT
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// (v16i8/v8i8).
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Match = DAG.getNode(ISD::SIGN_EXTEND, dl, OpContainerVT, Match);
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Match = convertFromScalableVector(DAG, Op1VT, Match);
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return DAG.getNode(ISD::TRUNCATE, dl, ResVT, Match);
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}
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SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op,
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SelectionDAG &DAG) const {
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unsigned IntNo = Op.getConstantOperandVal(1);
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@ -6383,6 +6462,9 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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DAG.getNode(AArch64ISD::CTTZ_ELTS, dl, MVT::i64, CttzOp);
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return DAG.getZExtOrTrunc(NewCttzElts, dl, Op.getValueType());
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}
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case Intrinsic::experimental_vector_match: {
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return LowerVectorMatch(Op, DAG);
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}
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}
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}
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@ -27153,6 +27235,7 @@ void AArch64TargetLowering::ReplaceNodeResults(
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Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
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return;
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}
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case Intrinsic::experimental_vector_match:
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case Intrinsic::get_active_lane_mask: {
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if (!VT.isFixedLengthVector() || VT.getVectorElementType() != MVT::i1)
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return;
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@ -985,6 +985,8 @@ public:
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bool shouldExpandCttzElements(EVT VT) const override;
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bool shouldExpandVectorMatch(EVT VT, unsigned SearchSize) const override;
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/// If a change in streaming mode is required on entry to/return from a
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/// function call it emits and returns the corresponding SMSTART or SMSTOP
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/// node. \p Condition should be one of the enum values from
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542
llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
Normal file
542
llvm/test/CodeGen/AArch64/intrinsic-vector-match-sve2.ll
Normal file
@ -0,0 +1,542 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=aarch64 < %s -o - | FileCheck %s
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define <vscale x 16 x i1> @match_nxv16i8_v1i8(<vscale x 16 x i8> %op1, <1 x i8> %op2, <vscale x 16 x i1> %mask) #0 {
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; CHECK-LABEL: match_nxv16i8_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mov z1.b, b1
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; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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%r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <1 x i8> %op2, <vscale x 16 x i1> %mask)
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ret <vscale x 16 x i1> %r
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}
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define <vscale x 16 x i1> @match_nxv16i8_v2i8(<vscale x 16 x i8> %op1, <2 x i8> %op2, <vscale x 16 x i1> %mask) #0 {
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; CHECK-LABEL: match_nxv16i8_v2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-NEXT: mov w8, v1.s[1]
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; CHECK-NEXT: fmov w9, s1
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; CHECK-NEXT: ptrue p1.b
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; CHECK-NEXT: mov z2.b, w9
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; CHECK-NEXT: mov z1.b, w8
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; CHECK-NEXT: cmpeq p2.b, p1/z, z0.b, z1.b
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; CHECK-NEXT: cmpeq p1.b, p1/z, z0.b, z2.b
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; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
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; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
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; CHECK-NEXT: ret
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%r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <2 x i8> %op2, <vscale x 16 x i1> %mask)
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ret <vscale x 16 x i1> %r
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}
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define <vscale x 16 x i1> @match_nxv16i8_v4i8(<vscale x 16 x i8> %op1, <4 x i8> %op2, <vscale x 16 x i1> %mask) #0 {
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; CHECK-LABEL: match_nxv16i8_v4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: addvl sp, sp, #-1
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; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
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; CHECK-NEXT: umov w8, v1.h[1]
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; CHECK-NEXT: umov w9, v1.h[0]
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; CHECK-NEXT: umov w10, v1.h[2]
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; CHECK-NEXT: ptrue p1.b
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; CHECK-NEXT: mov z2.b, w8
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; CHECK-NEXT: mov z3.b, w9
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; CHECK-NEXT: umov w8, v1.h[3]
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; CHECK-NEXT: mov z1.b, w10
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; CHECK-NEXT: cmpeq p2.b, p1/z, z0.b, z2.b
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; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
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; CHECK-NEXT: mov z2.b, w8
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; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z1.b
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; CHECK-NEXT: cmpeq p1.b, p1/z, z0.b, z2.b
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; CHECK-NEXT: mov p2.b, p3/m, p3.b
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; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
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; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
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; CHECK-NEXT: mov p1.b, p2/m, p2.b
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; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
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; CHECK-NEXT: addvl sp, sp, #1
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; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <4 x i8> %op2, <vscale x 16 x i1> %mask)
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ret <vscale x 16 x i1> %r
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}
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define <vscale x 16 x i1> @match_nxv16i8_v8i8(<vscale x 16 x i8> %op1, <8 x i8> %op2, <vscale x 16 x i1> %mask) #0 {
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; CHECK-LABEL: match_nxv16i8_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
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; CHECK-NEXT: mov z1.d, d1
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; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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%r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <8 x i8> %op2, <vscale x 16 x i1> %mask)
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ret <vscale x 16 x i1> %r
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}
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define <vscale x 16 x i1> @match_nxv16i8_v16i8(<vscale x 16 x i8> %op1, <16 x i8> %op2, <vscale x 16 x i1> %mask) #0 {
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; CHECK-LABEL: match_nxv16i8_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
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; CHECK-NEXT: mov z1.q, q1
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; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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%r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <16 x i8> %op2, <vscale x 16 x i1> %mask)
|
||||
ret <vscale x 16 x i1> %r
|
||||
}
|
||||
|
||||
define <16 x i1> @match_v16i8_v1i8(<16 x i8> %op1, <1 x i8> %op2, <16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v16i8_v1i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
|
||||
; CHECK-NEXT: dup v1.16b, v1.b[0]
|
||||
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <1 x i8> %op2, <16 x i1> %mask)
|
||||
ret <16 x i1> %r
|
||||
}
|
||||
|
||||
define <16 x i1> @match_v16i8_v2i8(<16 x i8> %op1, <2 x i8> %op2, <16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v16i8_v2i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
|
||||
; CHECK-NEXT: dup v3.16b, v1.b[4]
|
||||
; CHECK-NEXT: dup v1.16b, v1.b[0]
|
||||
; CHECK-NEXT: cmeq v3.16b, v0.16b, v3.16b
|
||||
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: orr v0.16b, v0.16b, v3.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <2 x i8> %op2, <16 x i1> %mask)
|
||||
ret <16 x i1> %r
|
||||
}
|
||||
|
||||
define <16 x i1> @match_v16i8_v4i8(<16 x i8> %op1, <4 x i8> %op2, <16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v16i8_v4i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1
|
||||
; CHECK-NEXT: dup v3.16b, v1.b[2]
|
||||
; CHECK-NEXT: dup v4.16b, v1.b[0]
|
||||
; CHECK-NEXT: dup v5.16b, v1.b[4]
|
||||
; CHECK-NEXT: dup v1.16b, v1.b[6]
|
||||
; CHECK-NEXT: cmeq v3.16b, v0.16b, v3.16b
|
||||
; CHECK-NEXT: cmeq v4.16b, v0.16b, v4.16b
|
||||
; CHECK-NEXT: cmeq v5.16b, v0.16b, v5.16b
|
||||
; CHECK-NEXT: cmeq v0.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: orr v1.16b, v4.16b, v3.16b
|
||||
; CHECK-NEXT: orr v0.16b, v5.16b, v0.16b
|
||||
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <4 x i8> %op2, <16 x i1> %mask)
|
||||
ret <16 x i1> %r
|
||||
}
|
||||
|
||||
define <16 x i1> @match_v16i8_v8i8(<16 x i8> %op1, <8 x i8> %op2, <16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v16i8_v8i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: shl v2.16b, v2.16b, #7
|
||||
; CHECK-NEXT: ptrue p0.b, vl16
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: mov z1.d, d1
|
||||
; CHECK-NEXT: cmlt v2.16b, v2.16b, #0
|
||||
; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0
|
||||
; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <8 x i8> %op2, <16 x i1> %mask)
|
||||
ret <16 x i1> %r
|
||||
}
|
||||
|
||||
define <16 x i1> @match_v16i8_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v16i8_v16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: shl v2.16b, v2.16b, #7
|
||||
; CHECK-NEXT: ptrue p0.b, vl16
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: cmlt v2.16b, v2.16b, #0
|
||||
; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0
|
||||
; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask)
|
||||
ret <16 x i1> %r
|
||||
}
|
||||
|
||||
define <8 x i1> @match_v8i8_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v8i8_v8i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: shl v2.8b, v2.8b, #7
|
||||
; CHECK-NEXT: ptrue p0.b, vl8
|
||||
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: mov z1.d, d1
|
||||
; CHECK-NEXT: cmlt v2.8b, v2.8b, #0
|
||||
; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0
|
||||
; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <8 x i1> @llvm.experimental.vector.match(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask)
|
||||
ret <8 x i1> %r
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @match_nxv8i16_v8i16(<vscale x 8 x i16> %op1, <8 x i16> %op2, <vscale x 8 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_nxv8i16_v8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z1.q, q1
|
||||
; CHECK-NEXT: match p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <vscale x 8 x i1> @llvm.experimental.vector.match(<vscale x 8 x i16> %op1, <8 x i16> %op2, <vscale x 8 x i1> %mask)
|
||||
ret <vscale x 8 x i1> %r
|
||||
}
|
||||
|
||||
define <8 x i1> @match_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v8i16:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: ushll v2.8h, v2.8b, #0
|
||||
; CHECK-NEXT: ptrue p0.h, vl8
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
||||
; CHECK-NEXT: shl v2.8h, v2.8h, #15
|
||||
; CHECK-NEXT: cmlt v2.8h, v2.8h, #0
|
||||
; CHECK-NEXT: cmpne p0.h, p0/z, z2.h, #0
|
||||
; CHECK-NEXT: match p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff
|
||||
; CHECK-NEXT: xtn v0.8b, v0.8h
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <8 x i1> @llvm.experimental.vector.match(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask)
|
||||
ret <8 x i1> %r
|
||||
}
|
||||
|
||||
; Cases where op2 has more elements than op1.
|
||||
|
||||
define <8 x i1> @match_v8i8_v16i8(<8 x i8> %op1, <16 x i8> %op2, <8 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v8i8_v16i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: shl v2.8b, v2.8b, #7
|
||||
; CHECK-NEXT: ptrue p0.b, vl8
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
|
||||
; CHECK-NEXT: cmlt v2.8b, v2.8b, #0
|
||||
; CHECK-NEXT: cmpne p0.b, p0/z, z2.b, #0
|
||||
; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
|
||||
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <8 x i1> @llvm.experimental.vector.match(<8 x i8> %op1, <16 x i8> %op2, <8 x i1> %mask)
|
||||
ret <8 x i1> %r
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @match_nxv16i8_v32i8(<vscale x 16 x i8> %op1, <32 x i8> %op2, <vscale x 16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_nxv16i8_v32i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
|
||||
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
|
||||
; CHECK-NEXT: .cfi_offset w29, -16
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z3.b, z1.b[1]
|
||||
; CHECK-NEXT: mov z4.b, b1
|
||||
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
|
||||
; CHECK-NEXT: ptrue p1.b
|
||||
; CHECK-NEXT: mov z5.b, z1.b[2]
|
||||
; CHECK-NEXT: cmpeq p2.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: mov z3.b, z1.b[3]
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z5.b
|
||||
; CHECK-NEXT: mov z4.b, z1.b[4]
|
||||
; CHECK-NEXT: mov p2.b, p3/m, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z1.b[5]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: mov z4.b, z1.b[6]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z1.b[7]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: mov z4.b, z1.b[8]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z1.b[9]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: mov z4.b, z1.b[10]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z1.b[11]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: mov z4.b, z1.b[12]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z1.b[13]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: mov z4.b, z1.b[14]
|
||||
; CHECK-NEXT: mov z1.b, z1.b[15]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, b2
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z4.b
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[1]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[2]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[3]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[4]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[5]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[6]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[7]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[8]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[9]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[10]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[11]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[12]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[13]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: mov z3.b, z2.b[14]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: cmpeq p3.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: mov z1.b, z2.b[15]
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: cmpeq p4.b, p1/z, z0.b, z3.b
|
||||
; CHECK-NEXT: cmpeq p1.b, p1/z, z0.b, z1.b
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p3.b
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
|
||||
; CHECK-NEXT: mov p1.b, p2/m, p2.b
|
||||
; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <vscale x 16 x i1> @llvm.experimental.vector.match(<vscale x 16 x i8> %op1, <32 x i8> %op2, <vscale x 16 x i1> %mask)
|
||||
ret <vscale x 16 x i1> %r
|
||||
}
|
||||
|
||||
define <16 x i1> @match_v16i8_v32i8(<16 x i8> %op1, <32 x i8> %op2, <16 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v16i8_v32i8:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: dup v4.16b, v1.b[1]
|
||||
; CHECK-NEXT: dup v5.16b, v1.b[0]
|
||||
; CHECK-NEXT: dup v6.16b, v1.b[2]
|
||||
; CHECK-NEXT: dup v7.16b, v1.b[3]
|
||||
; CHECK-NEXT: dup v16.16b, v1.b[4]
|
||||
; CHECK-NEXT: dup v17.16b, v1.b[5]
|
||||
; CHECK-NEXT: dup v18.16b, v1.b[6]
|
||||
; CHECK-NEXT: dup v19.16b, v1.b[7]
|
||||
; CHECK-NEXT: dup v20.16b, v1.b[8]
|
||||
; CHECK-NEXT: cmeq v4.16b, v0.16b, v4.16b
|
||||
; CHECK-NEXT: cmeq v5.16b, v0.16b, v5.16b
|
||||
; CHECK-NEXT: cmeq v6.16b, v0.16b, v6.16b
|
||||
; CHECK-NEXT: cmeq v7.16b, v0.16b, v7.16b
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v16.16b
|
||||
; CHECK-NEXT: cmeq v17.16b, v0.16b, v17.16b
|
||||
; CHECK-NEXT: dup v21.16b, v2.b[7]
|
||||
; CHECK-NEXT: dup v22.16b, v1.b[10]
|
||||
; CHECK-NEXT: orr v4.16b, v5.16b, v4.16b
|
||||
; CHECK-NEXT: orr v5.16b, v6.16b, v7.16b
|
||||
; CHECK-NEXT: orr v6.16b, v16.16b, v17.16b
|
||||
; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: cmeq v17.16b, v0.16b, v20.16b
|
||||
; CHECK-NEXT: dup v18.16b, v1.b[9]
|
||||
; CHECK-NEXT: dup v19.16b, v1.b[11]
|
||||
; CHECK-NEXT: dup v20.16b, v1.b[12]
|
||||
; CHECK-NEXT: cmeq v22.16b, v0.16b, v22.16b
|
||||
; CHECK-NEXT: orr v4.16b, v4.16b, v5.16b
|
||||
; CHECK-NEXT: orr v5.16b, v6.16b, v7.16b
|
||||
; CHECK-NEXT: orr v6.16b, v16.16b, v17.16b
|
||||
; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b
|
||||
; CHECK-NEXT: dup v18.16b, v1.b[13]
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: cmeq v17.16b, v0.16b, v20.16b
|
||||
; CHECK-NEXT: dup v19.16b, v2.b[0]
|
||||
; CHECK-NEXT: dup v20.16b, v2.b[1]
|
||||
; CHECK-NEXT: orr v4.16b, v4.16b, v5.16b
|
||||
; CHECK-NEXT: dup v5.16b, v2.b[6]
|
||||
; CHECK-NEXT: orr v6.16b, v6.16b, v7.16b
|
||||
; CHECK-NEXT: orr v7.16b, v16.16b, v17.16b
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v18.16b
|
||||
; CHECK-NEXT: cmeq v17.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: cmeq v18.16b, v0.16b, v20.16b
|
||||
; CHECK-NEXT: dup v19.16b, v2.b[2]
|
||||
; CHECK-NEXT: cmeq v5.16b, v0.16b, v5.16b
|
||||
; CHECK-NEXT: cmeq v20.16b, v0.16b, v21.16b
|
||||
; CHECK-NEXT: dup v21.16b, v2.b[8]
|
||||
; CHECK-NEXT: orr v6.16b, v6.16b, v22.16b
|
||||
; CHECK-NEXT: orr v7.16b, v7.16b, v16.16b
|
||||
; CHECK-NEXT: dup v16.16b, v1.b[14]
|
||||
; CHECK-NEXT: dup v1.16b, v1.b[15]
|
||||
; CHECK-NEXT: orr v17.16b, v17.16b, v18.16b
|
||||
; CHECK-NEXT: cmeq v18.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: dup v19.16b, v2.b[3]
|
||||
; CHECK-NEXT: orr v5.16b, v5.16b, v20.16b
|
||||
; CHECK-NEXT: cmeq v20.16b, v0.16b, v21.16b
|
||||
; CHECK-NEXT: dup v21.16b, v2.b[9]
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v16.16b
|
||||
; CHECK-NEXT: cmeq v1.16b, v0.16b, v1.16b
|
||||
; CHECK-NEXT: orr v4.16b, v4.16b, v6.16b
|
||||
; CHECK-NEXT: orr v17.16b, v17.16b, v18.16b
|
||||
; CHECK-NEXT: cmeq v18.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: dup v19.16b, v2.b[4]
|
||||
; CHECK-NEXT: orr v5.16b, v5.16b, v20.16b
|
||||
; CHECK-NEXT: cmeq v20.16b, v0.16b, v21.16b
|
||||
; CHECK-NEXT: dup v21.16b, v2.b[10]
|
||||
; CHECK-NEXT: orr v7.16b, v7.16b, v16.16b
|
||||
; CHECK-NEXT: orr v16.16b, v17.16b, v18.16b
|
||||
; CHECK-NEXT: cmeq v17.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: dup v18.16b, v2.b[5]
|
||||
; CHECK-NEXT: orr v5.16b, v5.16b, v20.16b
|
||||
; CHECK-NEXT: cmeq v19.16b, v0.16b, v21.16b
|
||||
; CHECK-NEXT: dup v20.16b, v2.b[11]
|
||||
; CHECK-NEXT: orr v1.16b, v7.16b, v1.16b
|
||||
; CHECK-NEXT: orr v6.16b, v16.16b, v17.16b
|
||||
; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b
|
||||
; CHECK-NEXT: dup v17.16b, v2.b[12]
|
||||
; CHECK-NEXT: orr v5.16b, v5.16b, v19.16b
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v20.16b
|
||||
; CHECK-NEXT: dup v18.16b, v2.b[13]
|
||||
; CHECK-NEXT: dup v19.16b, v2.b[14]
|
||||
; CHECK-NEXT: orr v1.16b, v4.16b, v1.16b
|
||||
; CHECK-NEXT: dup v2.16b, v2.b[15]
|
||||
; CHECK-NEXT: orr v4.16b, v6.16b, v7.16b
|
||||
; CHECK-NEXT: cmeq v6.16b, v0.16b, v17.16b
|
||||
; CHECK-NEXT: orr v5.16b, v5.16b, v16.16b
|
||||
; CHECK-NEXT: cmeq v7.16b, v0.16b, v18.16b
|
||||
; CHECK-NEXT: cmeq v16.16b, v0.16b, v19.16b
|
||||
; CHECK-NEXT: cmeq v0.16b, v0.16b, v2.16b
|
||||
; CHECK-NEXT: orr v1.16b, v1.16b, v4.16b
|
||||
; CHECK-NEXT: orr v4.16b, v5.16b, v6.16b
|
||||
; CHECK-NEXT: orr v5.16b, v7.16b, v16.16b
|
||||
; CHECK-NEXT: orr v1.16b, v1.16b, v4.16b
|
||||
; CHECK-NEXT: orr v0.16b, v5.16b, v0.16b
|
||||
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
|
||||
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <16 x i1> @llvm.experimental.vector.match(<16 x i8> %op1, <32 x i8> %op2, <16 x i1> %mask)
|
||||
ret <16 x i1> %r
|
||||
}
|
||||
|
||||
; Data types not supported by MATCH.
|
||||
; Note: The cases for SVE could be made tighter.
|
||||
|
||||
define <vscale x 4 x i1> @match_nxv4xi32_v4i32(<vscale x 4 x i32> %op1, <4 x i32> %op2, <vscale x 4 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_nxv4xi32_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
||||
; CHECK-NEXT: addvl sp, sp, #-1
|
||||
; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
|
||||
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
|
||||
; CHECK-NEXT: .cfi_offset w29, -16
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z2.s, z1.s[1]
|
||||
; CHECK-NEXT: mov z3.s, s1
|
||||
; CHECK-NEXT: ptrue p1.s
|
||||
; CHECK-NEXT: mov z4.s, z1.s[2]
|
||||
; CHECK-NEXT: mov z1.s, z1.s[3]
|
||||
; CHECK-NEXT: cmpeq p2.s, p1/z, z0.s, z2.s
|
||||
; CHECK-NEXT: cmpeq p3.s, p1/z, z0.s, z3.s
|
||||
; CHECK-NEXT: cmpeq p4.s, p1/z, z0.s, z4.s
|
||||
; CHECK-NEXT: cmpeq p1.s, p1/z, z0.s, z1.s
|
||||
; CHECK-NEXT: mov p2.b, p3/m, p3.b
|
||||
; CHECK-NEXT: sel p2.b, p2, p2.b, p4.b
|
||||
; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Folded Reload
|
||||
; CHECK-NEXT: mov p1.b, p2/m, p2.b
|
||||
; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
|
||||
; CHECK-NEXT: addvl sp, sp, #1
|
||||
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <vscale x 4 x i1> @llvm.experimental.vector.match(<vscale x 4 x i32> %op1, <4 x i32> %op2, <vscale x 4 x i1> %mask)
|
||||
ret <vscale x 4 x i1> %r
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @match_nxv2xi64_v2i64(<vscale x 2 x i64> %op1, <2 x i64> %op2, <vscale x 2 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_nxv2xi64_v2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
||||
; CHECK-NEXT: mov z2.d, z1.d[1]
|
||||
; CHECK-NEXT: ptrue p1.d
|
||||
; CHECK-NEXT: mov z1.d, d1
|
||||
; CHECK-NEXT: cmpeq p2.d, p1/z, z0.d, z2.d
|
||||
; CHECK-NEXT: cmpeq p1.d, p1/z, z0.d, z1.d
|
||||
; CHECK-NEXT: sel p1.b, p1, p1.b, p2.b
|
||||
; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <vscale x 2 x i1> @llvm.experimental.vector.match(<vscale x 2 x i64> %op1, <2 x i64> %op2, <vscale x 2 x i1> %mask)
|
||||
ret <vscale x 2 x i1> %r
|
||||
}
|
||||
|
||||
define <4 x i1> @match_v4xi32_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v4xi32_v4i32:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: dup v3.4s, v1.s[1]
|
||||
; CHECK-NEXT: dup v4.4s, v1.s[0]
|
||||
; CHECK-NEXT: dup v5.4s, v1.s[2]
|
||||
; CHECK-NEXT: dup v1.4s, v1.s[3]
|
||||
; CHECK-NEXT: cmeq v3.4s, v0.4s, v3.4s
|
||||
; CHECK-NEXT: cmeq v4.4s, v0.4s, v4.4s
|
||||
; CHECK-NEXT: cmeq v5.4s, v0.4s, v5.4s
|
||||
; CHECK-NEXT: cmeq v0.4s, v0.4s, v1.4s
|
||||
; CHECK-NEXT: orr v1.16b, v4.16b, v3.16b
|
||||
; CHECK-NEXT: orr v0.16b, v5.16b, v0.16b
|
||||
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
|
||||
; CHECK-NEXT: xtn v0.4h, v0.4s
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <4 x i1> @llvm.experimental.vector.match(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask)
|
||||
ret <4 x i1> %r
|
||||
}
|
||||
|
||||
define <2 x i1> @match_v2xi64_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {
|
||||
; CHECK-LABEL: match_v2xi64_v2i64:
|
||||
; CHECK: // %bb.0:
|
||||
; CHECK-NEXT: dup v3.2d, v1.d[1]
|
||||
; CHECK-NEXT: dup v1.2d, v1.d[0]
|
||||
; CHECK-NEXT: cmeq v3.2d, v0.2d, v3.2d
|
||||
; CHECK-NEXT: cmeq v0.2d, v0.2d, v1.2d
|
||||
; CHECK-NEXT: orr v0.16b, v0.16b, v3.16b
|
||||
; CHECK-NEXT: xtn v0.2s, v0.2d
|
||||
; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
|
||||
; CHECK-NEXT: ret
|
||||
%r = tail call <2 x i1> @llvm.experimental.vector.match(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask)
|
||||
ret <2 x i1> %r
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+sve2" }
|
||||
Loading…
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Reference in New Issue
Block a user