534051 Commits

Author SHA1 Message Date
Björn Pettersson
51fe5d2c31
[InstCombine] Pre-commit tests related to ADDLIKE+GEP->GEP+GEP. NFC (#135154)
InstCombine can transform ADD+GEP into GEP+GEP. But those rewrites does
not currently trigger when the ADD is a disjoint OR (which happens to be
the canonical form for certain ADD operations). Add lit tests to show
that we are lacking such rewrites.

Also add a test case showing that we do not preserve "inbounds nuw",
"nusw nuw" and "nuw" when doing such transforms and the ADD/OR is
known to be NUW.
2025-04-14 09:33:59 +02:00
Akshat Oke
e29f986838
[CodeGen][NPM] Port RemoveLoadsIntoFakeUses to NPM (#130068) 2025-04-14 12:58:03 +05:30
Matthias Braun
ed96e4642c
AArch64: Allow ZEXT+COPY -> FMOV peephole for ZPR registers as well (#135436) 2025-04-14 00:19:09 -07:00
Ricardo Jesus
1df4af6cbc
Reapply "[AArch64][SVE] Pair SVE fill/spill into LDP/STP with -msve-vector-bits=128." (#135177)
Reapplies #134068.

The first patch was missing a check to prevent attempts to pair SVE
fill/spill with other Neon load/store instructions, which could happen
specifically if the Neon instruction was unscaled.
2025-04-14 08:18:56 +01:00
Jack Styles
53cd5cfc67
[Clang][ARM] Ensure FPU Features are parsed when targeting cc1as (#134612)
Previously, `cc1as` did not consider the Features that can be included
from a target's FPU. This could lead to a situation where assembly files
could not compile as cc1as did not know if a feature was supported.

With this change, all the features for the FPU will be passed to `cc1as`
as `-target-feature` lines. By making this change, it will enable
`+nosimd` to be functional, worked on in #130623, and fix a regression
introduced in 8fa0f0efce5fb81eb422e6d7eec74c66dafef4a3 so
armv7s-apple-darwin targets can utilise VFPv4 correctly.

---------

Co-authored-by: Martin Storsjö <martin@martin.st>
2025-04-14 08:15:42 +01:00
Fabian Ritter
cf188d650c
[AMDGPU] Avoid crashes for non-byte-sized types in PromoteAlloca (#134042)
This patch addresses three problems when promoting allocas to vectors:
- Element types with size < 1 byte in allocas with a vector type caused
  divisions by zero.
- Element types whose size doesn't match their AllocSize hit an assertion.
- Access types whose size doesn't match their AllocSize hit an assertion.

With this patch, we do not attempt to promote affected allocas to vectors. In
principle, we could handle these cases in PromoteAlloca, e.g., by truncating
and extending elements from/to their allocation size. It's however unclear if
we ever encounter such cases in practice, so that doesn't seem worth the added
complexity.

For SWDEV-511252
2025-04-14 09:13:54 +02:00
Simon Pilgrim
150e7b14f9 [X86] Add test coverage for #134602 2025-04-14 07:50:00 +01:00
Shao-Ce SUN
893cd69872
[RISCV][MC] Emit x8 as fp instead of s0 (#135500)
When emphasizing `X8`'s functionality related to Frame Pointer, this option can be passed.
2025-04-14 14:48:47 +08:00
Kazu Hirata
1380a8259e
[AMDGPU] Use llvm::find and llvm::find_if (NFC) (#135582) 2025-04-13 23:46:57 -07:00
Yingwei Zheng
e710a5a9f2
[InstCombine] Fold fneg/fabs patterns with ppc_f128 (#130557)
This patch is needed by
https://github.com/llvm/llvm-project/pull/130496.
2025-04-14 14:30:00 +08:00
Mel Chen
ffd5b14894
[LV] Add test cases for reverse accesses involving irregular types. nfc (#135139)
Add a test with irregular type to ensure the vector load/store
instructions are not generated.
2025-04-14 14:17:39 +08:00
Mel Chen
9df153bc14
[LV] Remove unused requiresScalarEpilogue function. nfc (#135341) 2025-04-14 14:16:04 +08:00
YunQiang Su
58b5df09dc
Clang: Add elementwise minnum/maxnum builtin functions (#129207)
With https://github.com/llvm/llvm-project/pull/112852, we claimed that
llvm.minnum and llvm.maxnum should treat +0.0>-0.0, while libc doesn't
require fmin(3)/fmax(3) for it.

To make llvm.minnum/llvm.maxnum easy to use, we define the builtin
functions for them, include
    __builtin_elementwise_minnum
    __builtin_elementwise_maxnum

All of them support _Float16, __bf16, float, double, long double.
2025-04-14 13:49:32 +08:00
Michael Buch
a3f8359410 [lldb][test] Fix NativePDB/inline_sites_live.cpp inlined frame format
Adjust after https://github.com/llvm/llvm-project/pull/135343
2025-04-14 06:31:50 +01:00
Michael Park
63e2963f4a
Support '-fmodule-file-home-is-cwd' for C++ modules. (#135147) 2025-04-13 22:29:27 -07:00
Pengcheng Wang
e57f4e8969 [RISCV][NFC] Make generated intrinsic records more human-readable (#133710)
We add comment markers and print enum names instead of numbers.

For required extensions, we print the feature list instead of raw
bits.

This recommits d0cf5cd which was reverted by 21ff45d.
2025-04-14 13:00:57 +08:00
Wang Pengcheng
21ff45dea1 Revert "[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)"
This reverts commit d0cf5cd5f9790dc21396936d076389c3be1a9599.

Error: "declaration of ‘clang::RISCV::RequiredExtensions
{anonymous}::SemaRecord::RequiredExtensions’ changes meaning of
‘RequiredExtensions’ [-fpermissive]"
2025-04-14 12:56:33 +08:00
Akshat Oke
b283ff7eb1
[CodeGen][NPM] Port BranchRelaxation to NPM (#130067)
This completes the PreEmitPasses.
2025-04-14 10:19:42 +05:30
Fangrui Song
2ff226ae2c MCAsmBackend,Hexagon: Remove MCRelaxableFragment from fixupNeedsRelaxationAdvanced
Among fixupNeedsRelaxationAdvanced (introduced by
https://reviews.llvm.org/D8217) targets, only Hexagon needs the
`MCRelaxableFragment` parameter (commit
86f218e7ec5d941b7785eaebcb8f4cad76db8a64) to get the instruction packet
(MCInst with sub-instruction operands).

As fixupNeedsRelaxationAdvanced follows mayNeedRelaxation, we can store
the MCInst in mayNeedRelaxation and eliminate the MCRelaxableFragment
parameter.

Follow-up to 7c83b7ef1796210451b839f4c58f2815f4aedfe5 that eliminates
the MCRelaxableFragment parameter from fixupNeedsRelaxation.
2025-04-13 21:45:29 -07:00
Kazu Hirata
47cbc8706c
[Scalar] Avoid repeated hash lookups (NFC) (#135585) 2025-04-13 21:24:39 -07:00
Pengcheng Wang
d0cf5cd5f9
[RISCV][NFC] Make generated intrinsic records more human-readable (#133710)
We add comment markers and print enum names instead of numbers.

For required extensions, we print the feature list instead of raw
bits.
2025-04-14 12:17:26 +08:00
Krzysztof Drewniak
5ecc0ef6b0
[mlir] Improve EnumProp, making it take an EnumInfo (#132349)
This commit improves the `EnumProp` class, causing it to wrap around an
`EnumInfo` just like` EnumAttr` does. This EnumProp also has logic for
converting to/from an integer attribute and for being read and written
as bitcode.

The following variants of `EnumProp` are provided:
- `EnumPropWithAttrForm` - an EnumProp that can be constructed from (and
will be converted to, if `storeInCustomAttribute` is true) a custom
attribute, like an `EnumAttr`, instead of a plain integer. This is meant
for backwards compatibility with code that uses enum attributes.

`NamedEnumProp` adds a "`mnemonic` `<` $enum `>`" syntax around the
enum, replicating a common pattern seen in MLIR printers and allowing
for reduced ambiguity.

`NamedEnumPropWithAttrForm` combines both of these extensions.

(Sadly, bytecode auto-upgrade is hampered by the lack of the ability to
optionally parse an attribute.)

Depends on #132148
2025-04-13 22:46:57 -05:00
Tianle Liu
e038c5401c
[LTO][Pipelines] Add 0 hot-caller threshold for SamplePGO + FullLTO (#135152)
If a hot callsite function is not inlined in the 1st build, inlining the
hot callsite in pre-link stage of SPGO 2nd build may lead to Function
Sample not found in profile file in link stage. It will miss some
profile info.
ThinLTO has already considered and dealed with it by setting
HotCallSiteThreshold to 0 to stop the inline. This patch just adds the
same processing for FullLTO.
2025-04-14 11:21:08 +08:00
Sergei Barannikov
7778a197e6
[MC] Remove unused MCAsmBackend::isMicroMips() method (NFC) (#135581)
The only use was removed by 4c892770.
2025-04-14 06:20:46 +03:00
Jim Lin
a32d4917c8 [RISCV] Clean up the code for isBareSimmNLsb0. NFC. 2025-04-14 10:39:34 +08:00
Phoebe Wang
ebba554a32
[X86][AVX10] Remove VAES and VPCLMULQDQ feature from AVX10.1 (#135489)
According to SDM, they require both VAES/VPCLMULQDQ and AVX10.1 CPUID
bits.

Fixes: #135394
2025-04-14 08:54:10 +08:00
Kazu Hirata
1f195afa57
[Sema] Use llvm::erase_if (NFC) (#135574) 2025-04-13 16:36:45 -07:00
Kazu Hirata
f1ba4bb805
[Target] Use llvm::append_range (NFC) (#135568) 2025-04-13 16:36:23 -07:00
Kazu Hirata
dc5178cc41
[CodeGen] Use llvm::append_range (NFC) (#135567) 2025-04-13 16:36:03 -07:00
Kazu Hirata
20d35fe5a5
[llvm] Use llvm::is_contained (NFC) (#135566) 2025-04-13 16:35:29 -07:00
Fangrui Song
5d87ebf3ad [MC] Refactor fixup evaluation and relocation generation
Follow-up to commits 5710759eb390c0d5274c2a4d43967282d7df1993
and 634f9a981571eae000c1adc311014c5c64486187

- Integrate `evaluateFixup` into `recordRelocation` and inline code
  within `MCAssembler::layout`, removing `handleFixup`.
- Update `fixupNeedsRelaxation` to bypass `shouldForceRelocation` when
  calling `evaluateFixup`, eliminating the `WasForced` workaround for
  RISC-V linker relaxation (https://reviews.llvm.org/D46350 ).
2025-04-13 16:22:20 -07:00
Michael Buch
af7a7ba4aa [lldb][Format][NFC] Factor FunctionNameWithArgs case out into helper function 2025-04-14 00:12:30 +01:00
Fangrui Song
634f9a9815 ARMAsmBackend: Use fixupNeedsRelaxationAdvanced. NFC
This prepares for the upcoming change to simplify relocation recording
in MCAssembler.

While both MCAssembler::fixupNeedsRelaxation and
MCAssembler::handleFixup call evaluateFixup and use
shouldForceRelocation, the shouldForceRelocation logic is not supposed
to be needed by MCAssembler::fixupNeedsRelaxation.

The ARM special cases for interworking branches
(https://reviews.llvm.org/D33436 and https://reviews.llvm.org/D33898)
break the assumption. Switch to fixupNeedsRelaxationAdvanced and
explicitly test the conditions.
2025-04-13 15:55:11 -07:00
Michael Buch
1e153b782e
[lldb][Format] Display only the inlined frame name in backtraces if available (#135343)
When a frame is inlined, LLDB will display its name in backtraces as
follows:
```
* thread #1, queue = 'com.apple.main-thread', stop reason = breakpoint 1.3
  * frame #0: 0x0000000100000398 a.out`func() [inlined] baz(x=10) at inline.cpp:1:42
    frame #1: 0x0000000100000398 a.out`func() [inlined] bar() at inline.cpp:2:37
    frame #2: 0x0000000100000398 a.out`func() at inline.cpp:4:15
    frame #3: 0x00000001000003c0 a.out`main at inline.cpp:7:5
    frame #4: 0x000000026eb29ab8 dyld`start + 6812
```
The longer the names get the more confusing this gets because the first
function name that appears is the parent frame. My assumption (which may
need some more surveying) is that for the majority of cases we only care
about the actual frame name (not the parent). So this patch removes all
the special logic that prints the parent frame.

Another quirk of the current format is that the inlined frame name does
not abide by the `${function.name-XXX}` format variables. We always just
print the raw demangled name. With this patch, we would format the
inlined frame name according to the `frame-format` setting (see the
test-cases).

If we really want to have the `parentFrame [inlined] inlinedFrame`
format, we could expose it through a new `frame-format` variable (e..g.,
`${function.inlined-at-name}` and let the user decide where to place
things.
2025-04-13 23:21:52 +01:00
Fangrui Song
5710759eb3 MCAsmBackend,X86: Pass MCValue to fixupNeedsRelaxationAdvanced. NFC
This parameter eliminates a redundant computation for VK_ABS8 in X86 and
reduces reliance on shouldForceRelocation in relaxation decisions.

Note: `local: jmp local@plt` relaxes JMP. This behavior depends on
fixupNeedsRelaxation calling shouldForceRelocation, which might change
in the future.
2025-04-13 15:20:53 -07:00
Michael Buch
52e45a79ad
[lldb][Language] Change GetFunctionDisplayName to take SymbolContext by reference (#135536)
Both the `CPlusPlusLanguage` plugins and the Swift language plugin
already assume the `sc != nullptr`. And all `FormatEntity` callsites of
`GetFunctionDisplayName` already check for nullptr before passing `sc`.
This patch makes this pre-condition explicit by changing the parameter
to `const SymbolContext &`. This will help with some upcoming changes in
this area.
2025-04-13 23:19:26 +01:00
Brox Chen
cbe8f3ad76
[AMDGPU][True16][MC] fix fmac_f16_t16 vop3 format (#135464)
add fmac_f16_t16_e64 to isfmac check to fix the vop3 format of
fmac_f16_t16 instruction
2025-04-13 18:10:31 -04:00
Nico Weber
425ccd50dc [gn] port 3de93015386f 2025-04-13 15:09:21 -07:00
Yoann Congal
3de9301538
[clangd] Add a build option to disable building dexp (#133124)
Building dexp on Debian 11 currently causes intermittent failures [0] [1].

Adding the CLANGD_BUILD_DEXP option to disable dexp from the build
allows Debian 11 users to build clang (albeit without the dexp tool).

This option is set to "Build Dexp" by default so, no change is expected
without manual setting.

[0]: https://bugzilla.yoctoproject.org/show_bug.cgi?id=15803
[1]: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1101322
2025-04-13 18:03:46 -04:00
Adrian Prantl
99df442df1 Skip test on Darwin 2025-04-13 14:40:41 -07:00
Kazu Hirata
87322c9039
[ObjCopy] Use llvm::reverse (NFC) (#135559) 2025-04-13 14:16:26 -07:00
Sayan Saha
543351babf
[tosa] : Re-enable PR #135429 with ASAN fix (#135560)
Removed the calls to `sizeOp` after replacing `SliceOp`:

```
// Remove const_shape size op when it no longer has use point.
Operation *sizeConstShape = sliceOp.getSize().getDefiningOp();
```

Turns out as part of canonicalization, trivially dead ops are removed
anyway, so the above piece of code isn't actually needed.
2025-04-13 17:05:28 -04:00
Matthew Devereau
91a205653e
[AArch64][SVE] Instcombine ptrue(all) to splat(i1) (#135016)
SVE Operations such as predicated loads become canonicalized to LLVM
masked loads, and doing the same for ptrue(all) to splat(1) creates
further optimization opportunities from generic LLVM IR passes.
2025-04-13 20:40:51 +01:00
Kazu Hirata
e555ccaa4d
[llvm] Call *Map::erase directly (NFC) (#135545) 2025-04-13 12:04:40 -07:00
Ivan Butygin
d893d129e6
[mlir] GPUToROCDL: Fix crashes with unsupported shuffle datatypes (#135504)
Calling `getIntOrFloatBitWidth` on non-int/float types (`gpu.shuffle`
also accepts vectors) will crash.
2025-04-13 20:26:19 +02:00
Fangrui Song
c0afb77c2a
RISCVAsmParser: Reject call foo@invalid
... instead of silently parsing and ignoring it without leaving an error
message.

While here, remove an unreachable `@plt`.

Pull Request: https://github.com/llvm/llvm-project/pull/135509
2025-04-13 11:07:25 -07:00
Timm Baeder
974bda8f61
[clang][bytecode] Reject constexpr-unknown pointers from Inc ops (#135548)
We used to accept c++ as a known value here, causing wrong codegen.
2025-04-13 18:57:55 +02:00
Firas Khalil Khana
dd107b20da
Update LIBUNWIND_ENABLE_WERROR default value in BuildingLibunwind.rst (#135546)
`LIBUNWIND_ENABLE_WERROR` defaults to `OFF` according to
[CMakeLists.txt](https://github.com/llvm/llvm-project/blob/main/libunwind/CMakeLists.txt#L43).
2025-04-13 09:41:30 -07:00
Owen Pan
c41ef751f8
[clang-format] Treat lambda in braced init as inline (#135520)
Fix #125430
2025-04-13 09:02:46 -07:00
Owen Pan
5f11d64cfb
[clang-format] Fix a bug in AlignConsecutiveDeclarations (#135516)
Fix #109768
2025-04-13 09:01:37 -07:00