23 Commits

Author SHA1 Message Date
WuXinlong
42c36da9c9 [RISCV] Add MC support of RISCV Zcb Extension
This patch add the instructions of Zcb extension.

Instructions in zcb extensions shorten part of bit manipulation instructions.

Co-authored-by: Craig Topper <craig.topper@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D131141
2023-01-26 12:54:00 -08:00
Craig Topper
16c8833d32 [RISCV] Add Zcd and Zcf to RISCVUsage.rst. NFC 2023-01-25 22:08:16 -08:00
Kito Cheng
f4c887c3a8 [RISCV] Add H extension
`h` was the prefix of multi-letter extension name, but it become a
extension name in later RISC-V isa spec.

Fortunately we don't have any extension really defined is prefixed
with `h`, so we can just change that.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136817
2023-01-10 09:52:03 +08:00
Piyou Chen
20a1dcf572 [RISCV][NFC] Update RISCVUsage.rst for Svnapot extension
Note: Support Svnapot extension in https://reviews.llvm.org/D136570

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D136816
2023-01-04 18:44:41 -08:00
Yeting Kuo
bd9c0f082b [RISCV] Add Svpbmt extension support.
Spec of Svpbmt: https://github.com/riscv/riscv-isa-manual/blob/master/src/supervisor.tex#L2399

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D140692
2022-12-28 23:57:54 -08:00
Jie Fu
00926c30be [RISCV] Fix typos in RISCVUsage.rst
Fix typos `riscv-toolchai-convention` --> `riscv-toolchain-convention`

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D140717
2022-12-28 16:33:41 +08:00
Jojo R
54752f3ff6 [RISCV] Implement assembler support for XTHeadVdot
This patch implements the T-Head vendor extensions (XTHeadVdot),
which is documented here, it's based on standard vector extension v1.0:
  https://github.com/T-head-Semi/thead-extension-spec
2022-12-26 19:05:22 +08:00
Philip Reames
780c539844 [RISCV] Implement assembler support for XVentanaCondOps
This change provides an implementation of the XVentanaCondOps vendor extension. This extension is defined in version 1.0.0 of the VTx-family custom instructions specification (https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf) by Ventana Micro Systems.

In addition to the technical contribution, this change is intended to be a test case for our vendor extension policy.

Once this lands, I plan to use this extension to prototype selection lowering to conditional moves. There's an RVI proposal in flight, and the expectation is that lowering to these and the new RVI instructions is likely to be substantially similar.

Differential Revision: https://reviews.llvm.org/D137350
2022-11-14 09:01:54 -08:00
Philip Reames
9395b98ba0 [RISCV][docs] Add some wording around vendor extensions
This adds an initial bit of policy around inclusion of vendor extensions. My intention here is to leave all of the actual decision making to a case by case decision on the regular sync calls, but to spell out some of the pieces we've discussed and (I think) have general agreement on.

Differential Revision: https://reviews.llvm.org/D136968
2022-11-01 09:33:32 -07:00
Piyou Chen
7d7940fd77 [RISCV] add svinval extension
1. Add the svinval extension support
2. Add the svinval Predicates for its instruction

Note: the svinval instructions defined in https://reviews.llvm.org/D117654

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D136571
2022-10-26 09:45:30 -07:00
Craig Topper
52708be182 [RISCV] Remove support for the unratified Zbe, Zbf, and Zbm extensions.
These extensions do not appear to be on their way to ratification.
2022-09-22 13:04:41 -07:00
Craig Topper
182aa0cbe0 [RISCV] Remove support for the unratified Zbp extension.
This extension does not appear to be on its way to ratification.

Still need some follow up to simplify the RISCVISD nodes.
2022-09-21 21:22:42 -07:00
Craig Topper
70a64fe7b1 [RISCV] Remove support for the unratified Zbt extension.
This extension does not appear to be on its way to ratification.

Out of the unratified bitmanip extensions, this one had the
largest impact on the compiler.

Posting this patch to start a discussion about whether we should
remove these extensions. We'll talk more at the RISC-V sync meeting this
Thursday.

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D133834
2022-09-20 20:26:48 -07:00
Philip Reames
eda2af575f [RISCV][MC] Add support for experimental Zawrs extension
This implements experimental support for the Zawrs extension as specified here: https://github.com/riscv/riscv-zawrs/releases/download/V1.0-rc3/Zawrs.pdf. Despite the 1.0 version name, this has not been ratified and there was a major change to proposed specification between rc2 and rc3.  Once this is ratified, it'll move out of experimental status.

This change adds assembly support, but does not include C language or IR intrinsics. We can decide if we want them, and handle that in a separate patch.

Differential Revision: https://reviews.llvm.org/D133443
2022-09-20 10:15:11 -07:00
Aaron Ballman
55d626f852 Fix LLVM sphinx build
Addresses the issue found by:
https://lab.llvm.org/buildbot/#/builders/30/builds/25791

We can use anonymous references rather than explicit ones.
2022-09-09 07:55:12 -04:00
Philip Reames
c6d304aff3 [docs][RISCV] Add links to respective notes 2022-09-08 16:35:49 -07:00
Philip Reames
3757ef2e66 Fix a warning caught by llvm-sphinx-docs 2022-09-08 16:22:50 -07:00
Philip Reames
580f725d48 [docs] Fix a rebase error in 194900f 2022-09-08 16:04:03 -07:00
Philip Reames
194900fc24 [docs][RISCV] Document status of scalar crypto extensions
This is based on a somewhat subjective review of the in-tree support, and where I thought further work was needed before I'd consider these "done".  See the review for some discussion around what is left in terms of pattern matching.

Differential Revision: https://reviews.llvm.org/D133373
2022-09-08 15:55:10 -07:00
Philip Reames
44e74d8623 [docs][RISCV] Document status of assorted extensions
Sorry, there's no real theme to this. It's simply the rest of the extensions we implement which don't need individual discussion.

Differential Revision: https://reviews.llvm.org/D133529
2022-09-08 15:55:10 -07:00
Philip Reames
be442d2f12 [docs][RISCV] Document experimental extensions
This adds a description of the currently existing experimental extensions. I took all information about versions and specifications from either the original commits, or current code. I'm not terribly familiar with any of these, so double checking my facts is much appreciated.

Differential Revision: https://reviews.llvm.org/D133214
2022-09-08 12:26:16 -07:00
Philip Reames
10a74262ca [docs][RISCV] Document status of Zicpo(m,p,z) extensions
Unless I missed something when checking, we only support these in assembly. Given that, documenting them is a good opportunity to define support levels which will be useful for other extensions as well.

Differential Revision: https://reviews.llvm.org/D133372
2022-09-06 13:36:35 -07:00
Philip Reames
7f2b016b82 [docs] Add a RISC-V Usage page
This follows the pattern set by e.g. SPIR-V, AMDGPU, and WebAssembly.

For the moment, this page is fairly minimal stub. I mostly want a place to record which extensions we support, and when that support is not complete, a central place to note that. I'm deliberately starting with a subset of extensions which are pretty straight forward with only one case needing a detail note.

I figure the partial support cases are going to need a bunch of discussion, and having each of them in their own review seemed worthwhile. Similarly, the experimental extensions probably fall into the same bucket of triggering a bunch of review discussion.

Differential Revision: https://reviews.llvm.org/D133063
2022-09-06 12:12:07 -07:00