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497 Commits

Author SHA1 Message Date
Logan Chien
c6fd820937 Rename ANDROIDEABI to Android. 
Most of the code guarded with ANDROIDEABI are not
ARM-specific, and having no relation with arm-eabi.
Thus, it will be more natural to call this
environment "Android" instead of "ANDROIDEABI".

Note: We are not using ANDROID because several projects
are using "-DANDROID" as the conditional compilation
flag.

llvm-svn: 163088
 2012-09-02 09:30:11 +00:00
Simon Atanasyan
c6a0be00ab Define __mips64 / __mips64__ macros for MIPS 64-bit targets. 
The patch suggested by Brad Smith.

llvm-svn: 162858
 2012-08-29 20:50:11 +00:00
Simon Atanasyan
16ee0057ab Use getTargetDefines() virtual function in MipsTargetInfoBase successors 
to define all macros for MIPS targets. Remove redundant virtual function
getArchDefines(). Two virtual functions for this task are really too much.

llvm-svn: 162853
 2012-08-29 19:59:32 +00:00
Simon Atanasyan
683535bbdd Factor out MIPS macro definitions common for all MIPS targets. 
llvm-svn: 162852
 2012-08-29 19:14:58 +00:00
Simon Atanasyan
5a0642fdc1 Define _MIPS_ARCH and _MIPS_ARCH_<cpu name> macros for MIPS targets. 
The patch suggested by Logan Chien.

llvm-svn: 162840
 2012-08-29 15:17:29 +00:00
Eric Christopher
c34d391ca2 Remove FIXME, the constraints contain more options than the 
current available documentation.

llvm-svn: 162065
 2012-08-16 23:50:43 +00:00
Eric Christopher
9e49188a01 Add a missing 'break' to ensure that we reject inline assembly 
constraints we don't recognize.

llvm-svn: 162064
 2012-08-16 23:50:41 +00:00
Dylan Noblesmith
8d48c8c675 Frontend: define _LP64 in a target-independent way 
Instead of adding it to each individual subclass in
Targets.cpp, simply check the appropriate target
values.

Where before it was only on x86_64 and ppc64, it's now
also defined on mips64 and nvptx64.

Also add a bunch of negative tests to ensure it is *not*
defined on any other architectures while we're here.

llvm-svn: 161685
 2012-08-10 19:12:37 +00:00
Eli Friedman
9fa2885522 clang support for Bitrig (an OpenBSD fork); patch by David Hill. 
llvm-svn: 161546
 2012-08-08 23:57:20 +00:00
Hans Wennborg
29fbe3e0d7 Revert part of r161175 which was wrong for OpenBSD's PowerPC target. 
Contributed by Brad Smith <brad@comstyle.com>

llvm-svn: 161481
 2012-08-08 08:41:02 +00:00
Hans Wennborg
0bb8462bf7 Add OpenBSD arch targets for powerpc, arm, mips64, mips64el and sparc. 
Contributed by Brad Smith <brad@comstyle.com>

llvm-svn: 161175
 2012-08-02 13:45:48 +00:00
Hans Wennborg
1241731803 TLS is not supported on OpenBSD 
This fixes PR13502 and adds a test to keep track of which
targets support TLS and which do not.

llvm-svn: 161124
 2012-08-01 18:53:19 +00:00
Chad Rosier
cc40ea7f9a Add a per target max vector alignment field (e.g., 32-byte alignment for x86 due to 
AVX).  Currently, if no aligned attribute is specified the alignment of a vector is
inferred from its size.  Thus, very large vectors will be over-aligned with no 
benefit.  Target owners should set this target max.

llvm-svn: 160209
 2012-07-13 23:57:43 +00:00
Justin Holewinski
5fafdd9d1d Fix handling of curly braces in NVPTX inline asm 
Fixes bug 13322

Patch by Dmitry Mikushin

llvm-svn: 160050
 2012-07-11 15:34:55 +00:00
Benjamin Kramer
1e250395fa Wire up -mrdrnd for X86. 
For some reason GCC decided to call the feature rdrnd instead of rdrand,
which requires translating it for LLVM.

llvm-svn: 159897
 2012-07-07 09:39:18 +00:00
Benjamin Kramer
b2c42807a4 Remove unreachable default case to pacify clang's -Wcovered-switch-default. 
llvm-svn: 159829
 2012-07-06 15:27:25 +00:00
Simon Atanasyan
9780e4a2bb MIPS: Define __mips_dsp_rev / __mips_dspr2 / __mips_dsp macros 
if -mdsp or -mdspr2 options are provided.

llvm-svn: 159774
 2012-07-05 20:16:22 +00:00
Simon Atanasyan
9c6f1f7f23 MIPS: Add -mdsp/-mno-dsp and -mdspr2/-mno-dspr2 command line options support. 
llvm-svn: 159769
 2012-07-05 19:23:00 +00:00
Simon Atanasyan
72244b6e4f MIPS: Define __mips16 macro if -mips16 option is provided. 
llvm-svn: 159753
 2012-07-05 16:06:06 +00:00
Simon Atanasyan
9f444d5a1b MIPS: Replace the pair of boolean flags by enumeration to hold selected float ABI. 
llvm-svn: 159752
 2012-07-05 15:32:46 +00:00
Simon Atanasyan
6f23fa0f18 MIPS: Add -mips16 / -mno-mips16 command line support. 
llvm-svn: 159747
 2012-07-05 14:19:39 +00:00
Hal Finkel
6b984f084c Add additional architecture defines for PPC targets. 
Patch by Andy Gibbs.

llvm-svn: 159665
 2012-07-03 16:51:04 +00:00
Simon Atanasyan
07ce7d8fb5 Support MIPS DSP Rev1 intrinsics. 
This patch was reviewed in the llvm-commits list by Jim Grosbach.

llvm-svn: 159366
 2012-06-28 18:23:16 +00:00
Meador Inge
5d3fb22bac Explicitly build __builtin_va_list. 
The target specific __builtin_va_list types are now explicitly built instead
of injecting strings into the preprocessor input.

llvm-svn: 158592
 2012-06-16 03:34:49 +00:00
Hal Finkel
8eb5928514 Add PPC support for translating gcc-style -mcpu options into LLVM -target-cpu options. 
This functionality is based on what is done on ARM, and enables selecting PPC CPUs
in a way compatible with gcc's driver. Also, mirroring gcc (and what is done on x86),
-mcpu=native support was added. This uses the host cpu detection from LLVM
(which will also soon be updated by refactoring code currently in backend).

In order for this to work, the target needs a list of valid CPUs -- we now accept all CPUs accepted by LLVM.
A few preprocessor defines for common CPU types have been added.

llvm-svn: 158334
 2012-06-11 22:35:19 +00:00
Craig Topper
f561a9562d Add XOP feature flag. 
llvm-svn: 158284
 2012-06-09 22:24:14 +00:00
Simon Atanasyan
d3d173ddca Mips: Define __mips_hard_float macro additional to __mips_single_float 
when single float ABI is selected.

llvm-svn: 157996
 2012-06-05 13:06:56 +00:00
Craig Topper
12c9df3a9d Make disabling SSE levels also disable AVX and FMA. 
llvm-svn: 157907
 2012-06-03 22:23:42 +00:00
Craig Topper
1e9e01fabf Make AES and PCLMUL features imply SSE2 as that's needed to get the right types defined. 
llvm-svn: 157906
 2012-06-03 21:56:22 +00:00
Craig Topper
bba778bfd5 Add fma feature flag for Intel FMA instructions. 
llvm-svn: 157904
 2012-06-03 21:46:30 +00:00
Craig Topper
3f122a7636 Add builtin for pclmulqdq instruction. 
llvm-svn: 157733
 2012-05-31 05:18:48 +00:00
Craig Topper
9ee12508ca SSE4A should not imply LZCNT and POPCNT. FMA4 should imply SSE4A. Add missing break at the end of btver1 feature list. 
llvm-svn: 157680
 2012-05-30 05:54:54 +00:00
Benjamin Kramer
8ac9c22391 Define __SSE4A__ when targeting new AMD CPUs. 
This doesn't really fit the existing SSELevel so it gets an extra flag.

llvm-svn: 157630
 2012-05-29 17:48:39 +00:00
Roman Divacky
67030280f9 Sparc is bigendian. 
llvm-svn: 157626
 2012-05-29 16:10:50 +00:00
Justin Holewinski
83e9668133 Replace PTX back-end with NVPTX back-end in all places where Clang cares 
NV_CONTRIB

llvm-svn: 157403
 2012-05-24 17:43:12 +00:00
Peter Collingbourne
c947aaeeae Teach Clang about the NVPTX backend. 
llvm-svn: 157173
 2012-05-20 23:28:41 +00:00
Peter Collingbourne
f44bdf9c5f CUDA: add CodeGen support for global variable address spaces. 
Because in CUDA types do not have associated address spaces,
globals are declared in their "native" address space, and accessed
by bitcasting the pointer to address space 0.  This relies on address
space 0 being a unified address space.

llvm-svn: 157167
 2012-05-20 21:08:35 +00:00
Sirish Pande
11ebc4ed1b Hexagon V5 FP support. 
llvm-svn: 156567
 2012-05-10 20:19:54 +00:00
Craig Topper
eb590aa956 Enable AVX on AMD Bulldozer processors. 
llvm-svn: 155900
 2012-05-01 07:18:03 +00:00
Evgeniy Stepanov
94dc4c9783 Define __ANDROID__ macro on -androideabi targets. 
llvm-svn: 155632
 2012-04-26 12:08:09 +00:00
Craig Topper
5f365e94c3 Enable AVX/AVX2 for Sandy Bridge, Ivy Bridge, and Haswell CPUs. 
llvm-svn: 155624
 2012-04-26 07:31:30 +00:00
Chris Lattner
024e12df52 OpenBSD: Remove incorrect -pthread preprocessor define _POSIX_THREADS and replace 
with _REENTRANT. Also remove undef _POSIX_THREADS in phread.h.

Patch by Brad Smith!

llvm-svn: 155535
 2012-04-25 06:12:24 +00:00
Chandler Carruth
70ac923ebc Revert r155363, due to the underlying patches in LLVM causing regression 
test suite failures.

llvm-svn: 155371
 2012-04-23 18:25:40 +00:00
Sirish Pande
7039d0eaee Hexagon V5 (floating point) support in cfe. 
llvm-svn: 155363
 2012-04-23 17:48:57 +00:00
Chandler Carruth
b8ae76037a Revert some Hexagon builtin commits to match reverts done to LLVM in 
r155047. See the LLVM log for the primary motivation:
  http://llvm.org/viewvc/llvm-project?rev=155047&view=rev

Primary commit r154828:
  - Several issues were raised in review, and fixed in subsequent
    commits.
  - Follow-up commits also reverted, and which should be folded into the
    original before reposting:
    - r154837: Re-add the 'undef BUILTIN' thing to fix the build.
    - r154928: Fix build warnings, re-add (and correct) header and
      license
    - r154937: Typo fix.

Please resubmit this patch with the relevant LLVM resubmission.

llvm-svn: 155048
 2012-04-18 21:32:25 +00:00
Simon Atanasyan
296a7bb49f MIPS: Followup to r154606. Expand list of accepted MIPS target features in the MipsTargetInfoBase::setFeatureEnabled() routine. 
llvm-svn: 154998
 2012-04-18 12:00:11 +00:00
Sirish Pande
f02eebef2a Hexagon V5(Floating Point) support. 
llvm-svn: 154828
 2012-04-16 17:04:05 +00:00
Simon Atanasyan
ce74e9d896 MIPS: Initialize MIPS CPU's name by default value. 
Otherwise MipsTargetInfoBase::getDefaultFeatures() might return an invalid
features set with an empty feature name.

llvm-svn: 154606
 2012-04-12 19:59:24 +00:00
Simon Atanasyan
26f19678b6 Move some MIPS target macro definitions from class Mips32TargetInfoBase 
to the base class MipsTargetInfoBase. These macros are applicable for both
32/64-bits targets.

llvm-svn: 154116
 2012-04-05 19:28:31 +00:00
Chad Rosier
1f0e52e361 [driver] Create a new -mfpmath= option, which is used to control whether clang 
uses Neon instructions for single-precision FP.

-mfpmath=neon is analogous to passing llc -mattr=+neonfp.
-mfpmath=[vfp|vfp2|vfp3|vfp4] is analogous to passing llc -mattr=-neonfp.

rdar://11108618

llvm-svn: 154046
 2012-04-04 20:39:32 +00:00