mirrors/llvm-project
0
0
Fork 0
mirror of https://github.com/llvm/llvm-project.git synced 2025-05-03 01:56:07 +00:00
Code Issues Projects Releases Wiki Activity
285,835 Commits 1,258 Branches 288 Tags
Commit Graph

219 Commits

Author SHA1 Message Date
Craig Topper
66c20f344e Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
llvm-svn: 198336
 2014-01-02 19:12:10 +00:00
Craig Topper
fae226c67e Remove unused HasFROperands field from disassembler. 
llvm-svn: 198332
 2014-01-02 18:44:21 +00:00
Craig Topper
eabdbcb8a9 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
llvm-svn: 198327
 2014-01-02 18:20:48 +00:00
Craig Topper
a941d2b08e Remove unnecessary stirng comparison from disassembler. 
llvm-svn: 198325
 2014-01-02 17:41:40 +00:00
Craig Topper
9dd48c8ed4 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Craig Topper
83b7e24b76 Remove unused function argument. 
llvm-svn: 198291
 2014-01-02 03:58:45 +00:00
Craig Topper
3321c99a06 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
llvm-svn: 198284
 2014-01-01 21:52:57 +00:00
Craig Topper
9155118602 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
llvm-svn: 198278
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Craig Topper
623b0d64b3 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198276
 2014-01-01 14:22:37 +00:00
Craig Topper
e98c8cb9f0 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
llvm-svn: 198265
 2013-12-31 17:21:44 +00:00
Craig Topper
0e21bca6dd Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198238
 2013-12-30 19:16:48 +00:00
Craig Topper
6d776e2660 Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change. 
llvm-svn: 198226
 2013-12-30 17:37:10 +00:00
Eric Christopher
c0a5aaeab0 [x86] Rename In32BitMode predicate to Not64BitMode 
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

llvm-svn: 197768
 2013-12-20 02:04:49 +00:00
Elena Demikhovsky
47fc44e52e AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Craig Topper
a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
llvm-svn: 192567
 2013-10-14 04:55:01 +00:00
Craig Topper
88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Craig Topper
aab53e7785 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
llvm-svn: 192522
 2013-10-12 04:46:18 +00:00
Craig Topper
81034928c6 Remove another unnecessary filter from the disassembler. 
llvm-svn: 192425
 2013-10-11 06:59:57 +00:00
Craig Topper
e1ceeb40c1 Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. 
llvm-svn: 192339
 2013-10-10 04:26:52 +00:00
Craig Topper
2d0d180ab4 More x86 disassembler filtering cleanup. 
llvm-svn: 192279
 2013-10-09 06:12:53 +00:00
Craig Topper
043d749ba3 Remove some old filters from the x86 disassembler table builder. 
llvm-svn: 192275
 2013-10-09 05:02:29 +00:00
Craig Topper
a984729f8a Remove unneeded MMX instruction definition by moving pattern to an equivalent instruction definition and removing the filtering from the disassembler table building. 
llvm-svn: 192175
 2013-10-08 06:30:39 +00:00
Craig Topper
72c8cd7bc3 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
llvm-svn: 192171
 2013-10-08 05:53:50 +00:00
Craig Topper
07ad1b23bb Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
llvm-svn: 192090
 2013-10-07 07:19:47 +00:00
Craig Topper
2658d89728 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
llvm-svn: 192086
 2013-10-07 04:28:06 +00:00
Craig Topper
9e3e38ae3f Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Elena Demikhovsky
c35219e3ee AVX-512: Added masked SHIFT commands, more encoding tests 
llvm-svn: 189005
 2013-08-22 12:18:28 +00:00
Craig Topper
9469e906a5 Remove use of sprintf added to X86 disassembler tablegen code. Send message with instruction name to errs() instead and use a generic message for the llvm_unreachable. Consistent with other places in this file. 
llvm-svn: 187333
 2013-07-28 21:28:02 +00:00
Elena Demikhovsky
baf51e3e61 fixed compilation issue 
llvm-svn: 187325
 2013-07-28 08:45:12 +00:00
Elena Demikhovsky
003e7d73b9 Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324
 2013-07-28 08:28:38 +00:00
Stefanus Du Toit
8811ad4f81 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.

llvm-svn: 184207
 2013-06-18 17:08:10 +00:00
Michael Liao
95d9440348 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.

llvm-svn: 179266
 2013-04-11 04:52:28 +00:00
Dave Zarzycki
656e8515fc x86 -- add the XTEST instruction 
llvm-svn: 177888
 2013-03-25 18:59:43 +00:00
Kevin Enderby
f15856ebb4 Fixes disassembler crashes on 2013 Haswell RTM instructions. 
rdar://13318048

llvm-svn: 176828
 2013-03-11 21:17:13 +00:00
Kay Tiong Khoo
ab588efe42 Added 0x0D to 2-byte opcode extension table for prefetch* variants 
Fixed decode of existing 3dNow prefetchw instruction
Intel is scheduled to add a compatible prefetchw (same encoding) to future CPUs

llvm-svn: 174920
 2013-02-12 00:19:12 +00:00
Chandler Carruth
91d19d8e93 Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Michael Liao
73cffddb95 Add support of RTM from TSX extension 
- Add RTM code generation support throught 3 X86 intrinsics:
  xbegin()/xend() to start/end a transaction region, and xabort() to abort a
  tranaction region

llvm-svn: 167573
 2012-11-08 07:28:54 +00:00
Craig Topper
3f23c1a8b9 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Craig Topper
c30fdbc46c Add support for converting llvm.fma to fma4 instructions. 
llvm-svn: 162999
 2012-08-31 15:40:30 +00:00
Craig Topper
c6b7ef61f4 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code. 
llvm-svn: 160951
 2012-07-30 06:48:11 +00:00
Craig Topper
08ead0b14e Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly 
llvm-svn: 160950
 2012-07-30 06:27:19 +00:00
Craig Topper
6f4ad80dc8 Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already. 
llvm-svn: 160949
 2012-07-30 05:39:34 +00:00
Craig Topper
b58dc17025 Simplify code that filtered certain instructions in two different ways. No functional change. 
llvm-svn: 160948
 2012-07-30 05:10:05 +00:00
Craig Topper
60a58ac3e2 Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway. 
llvm-svn: 160946
 2012-07-30 04:53:00 +00:00
Craig Topper
ac172e225d Remove trailing whitespace. 
llvm-svn: 160945
 2012-07-30 04:48:12 +00:00
Craig Topper
c7690ac7ac Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms. 
llvm-svn: 160775
 2012-07-26 07:48:28 +00:00
Richard Trieu
9208abd7c3 Move around some enum elements so that lastMRM corrects gets assigned 56, which 
is one more that MRM_DF which is 55.  Previously, it held value 45, the same
as MRM_D0.

llvm-svn: 160465
 2012-07-18 23:04:22 +00:00
Craig Topper
01deb5f2df Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
llvm-svn: 160420
 2012-07-18 04:11:12 +00:00