20 Commits

Author SHA1 Message Date
Sanjin Sijaric
56391d6f84 [ARM64] [Windows] Follow MS X86_64 C++ ABI when passing structs
Summary: Microsoft's C++ object model for ARM64 is the same as that for X86_64.
For example, small structs with non-trivial copy constructors or virtual
function tables are passed indirectly.  Currently, they are passed in registers
when compiled with clang.

Reviewers: rnk, mstorsjo, TomTan, haripul, javed.absar

Reviewed By: rnk, mstorsjo

Subscribers: kristof.beyls, chrib, llvm-commits, cfe-commits

Differential Revision: https://reviews.llvm.org/D49770

llvm-svn: 338076
2018-07-26 22:18:28 +00:00
Martin Storsjo
17c0f721b9 [AArch64] Define TARGET_HEADER_BUILTIN
Without it, the new intrinsics became available for all language
variants. This was missed in SVN r337327.

llvm-svn: 337352
2018-07-18 06:15:09 +00:00
Joerg Sonnenberger
68c0210fa6 By popular demand, switch in64_t on NetBSD/AArch64 and NetBSD/PowerPC64
to long for consistency with other 64bit platforms.

llvm-svn: 337271
2018-07-17 12:33:19 +00:00
Junmo Park
4b9b9fb7a0 [AAch64] Add the __ARM_FEATURE_DOTPROD macro definition
This matches what GCC does.
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/aarch64/aarch64-c.c

Differential Revision: https://reviews.llvm.org/D45544

llvm-svn: 330229
2018-04-17 22:38:40 +00:00
Manoj Gupta
cb668d8512 [AArch64]: Add support for parsing rN registers.
Summary:
Allow rN registers to be simply parsed as correspoing xN registers.
The "register ... asm("rN")" is an command to the
compiler's register allocator, not an operand to any individual assembly
instruction. GCC documents this syntax as "...the name of the register
that should be used."

This is needed to support the changes in Linux kernel (see
https://lkml.org/lkml/2018/3/1/268 )

Note: This will add support only for the limited use case of
register ... asm("rN"). Any other uses that make rN leak into assembly
are not supported.

Reviewers: kristof.beyls, rengolin, peter.smith, t.p.northover

Reviewed By: peter.smith

Subscribers: javed.absar, eraman, cfe-commits, srhines

Differential Revision: https://reviews.llvm.org/D44815

llvm-svn: 328829
2018-03-29 21:11:15 +00:00
Sjoerd Meijer
87793e7599 [ARM] Pass half or i16 types for NEON intrinsics
For generating NEON intrinsics, this determines the NEON data type, and whether
it should be a half type or an i16 type. I.e., we always pass a half type for
AArch64, this hasn't changed, but now also for ARM but only when FullFP16 is
enabled, and i16 otherwise.

This is intended to be non-functional change, but together with the backend
work in D44538 which adds support for f16 vectors, this enables adding the
AArch32 FP16 (vector) intrinsics.

Differential Revision: https://reviews.llvm.org/D44561

llvm-svn: 327836
2018-03-19 13:22:49 +00:00
Erich Keane
3ec1743d0d Make march/target-cpu print a note with the list of valid values for ARM
When rejecting a march= or target-cpu command line parameter,
the message is quite lacking. This patch adds a note that prints
all possible values for the current target, if the target supports it.

This adds support for the ARM/AArch64 targets (more to come!). 

Differential Revision: https://reviews.llvm.org/D42978 

llvm-svn: 324673
2018-02-08 23:14:15 +00:00
Abderrazek Zaafrani
ce8746d178 [AArch64] Add ARMv8.2-A FP16 scalar intrinsics
https://reviews.llvm.org/D41792

llvm-svn: 323006
2018-01-19 23:11:18 +00:00
Benjamin Kramer
3a13ed60ba Avoid int to string conversion in Twine or raw_ostream contexts.
Some output changes from uppercase hex to lowercase hex, no other functionality change intended.

llvm-svn: 321526
2017-12-28 16:58:54 +00:00
Abderrazek Zaafrani
f58a132eef [AARch64] Add ARMv8.2-A FP16 vector intrinsics
Putting back the code that was reverted few weeks ago.

Differential Revision: https://reviews.llvm.org/D34161

llvm-svn: 321294
2017-12-21 19:20:01 +00:00
Martell Malone
051e966e49 [MINGW] normalize WIN32 macros
move _WIN64 and _WIN32 defines to lib/Basic/Targets/OSTargets.h
move WIN32, WIN64 and __MINGW64__ to addMinGWDefines

fixes __MINGW64__ not being defined for aarch64
adds WIN32 definition for x64

Reviewers: mstorsjo

Differential Revision: https://reviews.llvm.org/D40285

llvm-svn: 318755
2017-11-21 11:28:29 +00:00
Martin Storsjo
d8a44ed74c [COFF, ARM64] Add MS builtins __dmb, __dsb, __isb
Differential Revision: https://reviews.llvm.org/D38821

llvm-svn: 315567
2017-10-12 07:05:37 +00:00
Saleem Abdulrasool
729379a1e1 Driver: hoist the wchar_t handling to the driver
Move the logic for determining the `wchar_t` type information into the
driver.  Rather than passing the single bit of information of
`-fshort-wchar` indicate to the frontend the desired type of `wchar_t`
through a new `-cc1` option of `-fwchar-type` and indicate the
signedness through `-f{,no-}signed-wchar`.  This replicates the current
logic which was spread throughout Basic into the
`RenderCharacterOptions`.

Most of the changes to the tests are to ensure that the frontend uses
the correct type.  Add a new test set under `test/Driver/wchar_t.c` to
ensure that we calculate the proper types for the various cases.

llvm-svn: 315126
2017-10-06 23:09:55 +00:00
Saleem Abdulrasool
4d321336d0 Basic: support Preserve{Most,All} CC on Windows
Add support for the `preserve_mostcc` and `preserve_allcc` on Windows
x86_64 and AArch64.  This is used by Swift.

llvm-svn: 314236
2017-09-26 19:26:01 +00:00
Martin Storsjo
31cac7a67c [AArch64] Add support for a MinGW AArch64 target
Differential Revision: https://reviews.llvm.org/D36364

llvm-svn: 310798
2017-08-13 19:42:17 +00:00
Martin Storsjo
c85d26b0f3 [AArch64] Ignore stdcall and similar on aarch64/windows
This is similar to what's done on arm and x86_64, where
these calling conventions are silently ignored, as in
SVN r245076.

Differential Revision: https://reviews.llvm.org/D36105

llvm-svn: 310303
2017-08-07 20:52:04 +00:00
Martin Storsjo
588a3e5e6c [AArch64] Don't define __LP64__ when targeting Windows
Windows/ARM64 is a LLP64 environment, so don't set this default
define.

Differential Revision: https://reviews.llvm.org/D36098

llvm-svn: 309619
2017-07-31 20:40:53 +00:00
Florian Hahn
ef5bbd61da Update to use enum classes for various ARM *Kind enums
Summary: This updates the relevant Clang parts for the LLVM change D35882.

Reviewers: rengolin, chandlerc, javed.absar, rovka

Reviewed By: rovka

Subscribers: aemerson, cfe-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D35884

llvm-svn: 309289
2017-07-27 16:28:39 +00:00
Tim Northover
ad4c5db1ef AArch64 & ARM: move TargetInfo functions from .h to .cpp file. NFC.
Most of them are virtual anyway, and the few remaining ones can move to the
.cpp for consistency.

llvm-svn: 308898
2017-07-24 17:06:23 +00:00
Erich Keane
ebba592682 Break up Targets.cpp into a header/impl pair per target type[NFCI]
Targets.cpp is getting unwieldy, and even minor changes cause the entire thing 
to cause recompilation for everyone. This patch bites the bullet and breaks 
it up into a number of files.

I tended to keep function definitions in the class declaration unless it 
caused additional includes to be necessary. In those cases, I pulled it 
over into the .cpp file. Content is copy/paste for the most part, 
besides includes/format/etc.


Differential Revision: https://reviews.llvm.org/D35701

llvm-svn: 308791
2017-07-21 22:37:03 +00:00