15110 Commits

Author SHA1 Message Date
Craig Topper
009971a0d3
[TableGen] Accurately calculate where the source variable ops start in PseudoLoweringEmitter::emitLoweringEmitter. (#135465)
The code was using the number of source operands plus one. The plus one
seems to be an ARM specific value accounting for one of the source
operands having 2 sub operands. No other target in tree uses
PseudoLowering with variadic instructions so this worked.

This patch replaces it with a proper count of the number of sub operands
of all operands. While there I update the loop to use MIOperandNo so we
don't need to count up the sub operands as we go.
2025-04-12 10:00:56 -07:00
Craig Topper
6bea80e93f [TableGen] Remove unneeded FIXME. NFC
The message looks correct to me.
2025-04-11 21:37:35 -07:00
Nico Weber
957bd6aa32 [gn] port d1fd97737e90 2025-04-11 19:08:05 -04:00
LLVM GN Syncbot
cb974dcd77 [gn build] Port de5b099dd154 2025-04-11 17:48:57 +00:00
Nicolai Hähnle
9c31155ead
TableGen: Optimize super-register class computation (#134865)
Inferring super-register classes naively requires checking every
register class against every other register class and sub-register
index.
Each of those checks is itself a non-trivial operation on register sets.

Culling as many (RC, RC, SubIdx) triples as possible is important for
the running time of TableGen for architectures with complex sub-register
relations.

Use transitivity to cull many (RC, RC, SubIdx) triples. This
unfortunately requires us to complete the transitive closure of
super-register classes explicitly, but it still cuts down the running
time on AMDGPU substantially -- in some upcoming work in the
backend by more than half (in very rough measurements).

This changes the names of some of the inferred register classes, since
the order in which they are inferred changes. The names of the inferred
register classes become shorter, which reduces the size of the generated
files.

Replacing some uses of SmallPtrSet by DenseSet shaves off a few more
percent; there are hundreds of register classes in AMDGPU.

Tweaking the topological signature check to skip reigsters without
super-registers further helps skip register classes that have "pseudo"
registers in them whose sub- and super-register structure is trivial.
2025-04-10 12:00:08 -07:00
Nico Weber
dcb2ae126d [gn] port e10f67a8270c774 2025-04-10 07:50:13 -04:00
Nico Weber
4f64da1495 [gn build] Port 750da48b4aa5
The .h removals was done by the sync script. I manually cleaned up
the remaining removals based on the output of

    git show 750da48b4aa52f libcxx/include/CMakeLists.txt | rg '^- ' | rg -v '\.'
2025-04-09 09:23:11 -04:00
LLVM GN Syncbot
f46d6412eb [gn build] Port 96f95c9d89d8 2025-04-09 06:42:26 +00:00
Sudharsan Veeravalli
9b8f5340dd
Improve readability of <Target>GenCompressionInstEmitter. NFC (#134834)
Use indent() instead of manually indenting the code in the
CompressInstEmitter.cpp. Also modify the current indentation in a few
places.
2025-04-09 11:15:14 +05:30
Dirk Pranke
333f2c3341
[gn] Use exec_script_allowlist in //llvm/utils/gn/.gn (#134172)
This requires gn_version >= 2207. Run llvm/utils/gn/get.py to
update your GN binary if you hit the assert added in this commit.
2025-04-08 22:33:07 -04:00
Peter Collingbourne
bd2df7b076
gn build: Enable check-hwasan on aarch64 Linux.
Reviewers: aeubanks, vitalybuka

Reviewed By: vitalybuka

Pull Request: https://github.com/llvm/llvm-project/pull/134944
2025-04-08 16:15:14 -07:00
Peter Collingbourne
d3a9d471f7
gn build: Replace ${hwasan_name}-preinit with hwasan-preinit.
The driver only ever looks for the latter.

Reviewers: aeubanks

Reviewed By: aeubanks

Pull Request: https://github.com/llvm/llvm-project/pull/134943
2025-04-08 16:14:46 -07:00
Peter Collingbourne
93096bf830
gn build: Add hwasan_preinit.cpp to hwasan static library to match CMake.
Reviewers: aeubanks

Reviewed By: aeubanks

Pull Request: https://github.com/llvm/llvm-project/pull/134942
2025-04-08 16:14:19 -07:00
Peter Collingbourne
6010d5ba2b gn build: Port 2f1416bbcde8 more 2025-04-08 10:51:55 -07:00
Nico Weber
bb7ff134dc [gn] port 6c74fe9087 2025-04-08 12:03:45 -04:00
Nuno Lopes
b416e7f592 [CI] adjust the undef warning regex so it doesn't catch %undef in .ll files 2025-04-08 16:56:38 +01:00
Nico Weber
94b9d75c6d [gn] port 65813e0e94c04 2025-04-08 09:16:37 -04:00
Benjamin Maxwell
e1fc118f3a
[CI] Reduce false positives in undef checker (#134687)
Only check for diffs containing "undef" in .ll files, this prevents
comments like `// We should not have undef values...` triggering the
undef checker bot.
2025-04-08 09:53:33 +01:00
Peter Collingbourne
499930e38a gn build: Spell arm64 correctly. 2025-04-07 19:37:33 -07:00
Peter Collingbourne
9222607227
gn build: Add check-builtins target.
Tested on aarch64 Linux and x86_64 Linux.

Reviewers: aeubanks, nico

Reviewed By: aeubanks

Pull Request: https://github.com/llvm/llvm-project/pull/134482
2025-04-07 13:22:52 -07:00
LLVM GN Syncbot
78f624a0d4 [gn build] Port 7013b51548c0 2025-04-07 20:01:32 +00:00
LLVM GN Syncbot
e1f6e40b28 [gn build] Port 475cbf0ad6e7 2025-04-07 20:01:31 +00:00
LLVM GN Syncbot
06bf7a99fd [gn build] Port 1f72fa29ecb4 2025-04-07 20:01:30 +00:00
LLVM GN Syncbot
7d4cddadf2 [gn build] Port 0a1742708ddc 2025-04-07 20:01:29 +00:00
Nico Weber
1043f5cb0b [gn] port 16c84c4475b9 2025-04-07 13:30:59 -04:00
LLVM GN Syncbot
e2092a430a [gn build] Port da69eb75cbc6 2025-04-04 18:29:23 +00:00
LLVM GN Syncbot
22921540cd [gn build] Port 7d3dfc862d28 2025-04-04 18:29:22 +00:00
LLVM GN Syncbot
1d88cfcbb8 [gn build] Port 46e2c07fa28b 2025-04-04 18:29:21 +00:00
Nico Weber
d9bf390852 [gn] port 4a4d41e723a
...and add missing TargetsToBuild dep.
2025-04-04 13:52:09 -04:00
Nico Weber
8f6551935a [gn] Add a missing dependency
Needed after 6ee5e694bff
2025-04-04 13:32:36 -04:00
Nico Weber
6ee5e694bf [gn] port 10c6ebc4271 (-gen-clang-diags-compat-ids) 2025-04-04 13:25:41 -04:00
Fangrui Song
c9f6d26e04
[MC] Merge MCAsmLexer.{h,cpp} into AsmLexer.{h,cpp} (#134207)
2b11c7de4ae182496438e166cb6758d41b6e1740 introduced
`llvm/include/llvm/MC/MCAsmLexer.h` and made `AsmLexer` inherit from
`MCAsmLexer`, likely to allow target-specific parsers to depend solely
on `MCAsmLexer`. However, this separation now seems unnecessary and
confusing.

`MCAsmLexer` defines virtual functions with `AsmLexer` as its only
implementation, and `AsmLexer` itself has few extra public methods.

To simplify the codebase, this change merges MCAsmLexer.{h,cpp} into
AsmLexer.{h,cpp}. MCAsmLexer.h is temporarily kept as a forwarder.

Note: I doubt that a downstream lexer handling an assembly syntax
significantly different from the standard GNU Assembler syntax would
want to inherit from `MCAsmLexer`. Instead, it's more likely they'd
extend `AsmLexer` by adding new states and modifying its internal logic,
as seen with variables for MASM, M68k, and HLASM.
2025-04-03 19:22:45 -07:00
Pengcheng Wang
4986a79648
[TableGen] Emit llvm::is_contained for CheckOpcode predicate (#134057)
When the list is large, using `llvm::is_contained` is of higher
performance than a sequence of comparisons. When the list is small,
the `llvm::is_contained` can be inlined and unrolled, which has the
same effect as using a sequence of comparisons.

And the generated code is more readable.
2025-04-03 11:11:36 +08:00
Jon Roelofs
749c20b3e0
[LIT] Add a test for lit.Test.toMetricValue. NFC 2025-04-02 17:35:14 -07:00
George Burgess IV
a8585654c2
[llvm][utils] skip revert-checking reverts across branches (#134108)
e2ba1b6ffde4ec607342b1b746d1b57f0f04390a references that it reverts a
commit that's not a parent of e2ba1b6ffde4ec607342b1b746d1b57f0f04390a.

Functionally, this can (and demonstrably does) work(*), but from the
standpoint of the revert checker, it's nonsense. Print a `logging.error`
when it's detected.

Tested by running the revert checker against a commit range that
includes the aforementioned commit; the logging.error was fired
appropriately.

(*) - the specifics here are:
- the _SHA_ that was referenced was on a non-main branch, but
- the commit from the non-main branch was merged into the non-main
branch from main
- ...so the _functional_ commit being reverted was originally landed on
main, but the _SHA_ referenced from main was from a branch that was cut
before the reverted-commit was landed on main
2025-04-02 13:44:18 -07:00
Florian Hahn
3bdf9a0880
[EquivalenceClasses] Use SmallVector for deterministic iteration order. (#134075)
Currently iterators over EquivalenceClasses will iterate over std::set,
which guarantees the order specified by the comperator. Unfortunately in
many cases, EquivalenceClasses are used with pointers, so iterating over
std::set of pointers will not be deterministic across runs.

There are multiple places that explicitly try to sort the equivalence
classes before using them to try to get a deterministic order
(LowerTypeTests, SplitModule), but there are others that do not at the
moment and this can result at least in non-determinstic value naming in
Float2Int.

This patch updates EquivalenceClasses to keep track of all members via a
extra SmallVector and removes code from LowerTypeTests and SplitModule
to sort the classes before processing.

Overall it looks like compile-time slightly decreases in most cases, but
close to noise:

https://llvm-compile-time-tracker.com/compare.php?from=7d441d9892295a6eb8aaf481e1715f039f6f224f&to=b0c2ac67a88d3ef86987e2f82115ea0170675a17&stat=instructions

PR: https://github.com/llvm/llvm-project/pull/134075
2025-04-02 20:27:43 +01:00
Craig Topper
e020fc1895
[TableGen] Directly use SDNode functions to implement HasOneUse and HasNoUse. NFC (#133976)
The SDValue functions we were calling wrap SDNode functions we can call
directly.
2025-04-01 22:14:17 -07:00
Nico Weber
7b2b3faeb1 [gn build] Port 676755561d5a (ParseTests) 2025-04-01 15:34:00 -07:00
Nico Weber
86e66d2820 [gn] port 7003f7d23aeca 2025-04-01 14:36:50 -07:00
Matt Arsenault
f60eed9344
llvm-reduce: Add target-features-attr reduction (#133887)
Try to reduce individual subtarget features in the "target-features"
attribute. This attempts a textual removal of the fields in the string,
not a semantic removal. Typically there's a lot of redundant feature spam
in the feature list implied by the target-cpu (which I really wish clang
would stop emitting). If we could parse these out, we could easily drop
the fields without testing anything.
2025-04-02 00:03:43 +07:00
Florian Hahn
9e5bfbf77d
[EquivalenceClasses] Update member_begin to take ECValue (NFC).
Remove a level of indirection and update code to use range-based for
loops.
2025-04-01 09:28:46 +01:00
Craig Topper
40c859a704
[TableGen] Use size returned by encodeULEB128 to simplify some code. NFC (#133750)
We can use the length to insert all the bytes at once instead of
partially decoding them to insert one byte at a time.
2025-03-31 15:58:36 -07:00
LLVM GN Syncbot
b91f978647 [gn build] Port 50949ebf523c 2025-03-31 15:20:59 +00:00
Kazu Hirata
6257621f41
[llvm] Use llvm::append_range (NFC) (#133658) 2025-03-30 18:43:02 -07:00
Kazu Hirata
2c73711995
[TableGen] Use llvm::append_range (NFC) (#133649) 2025-03-30 12:21:38 -07:00
Tim Gymnich
1d0005a69a
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
- rename `GISelKnownBits` to `GISelValueTracking` to analyze more than
just `KnownBits` in the future
2025-03-29 11:51:29 +01:00
LLVM GN Syncbot
4324f236ac [gn build] Port c8a70f4c6e24 2025-03-28 23:58:46 +00:00
Tim Gymnich
049f179606
[Analysis][NFC] Extract KnownFPClass (#133457)
- extract KnownFPClass for future use inside of GISelKnownBits

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-03-28 18:10:02 +01:00
Jay Foad
a983c3b209
[TableGen] Make more use of CodeGenRegisterClass::EnumValue. NFC. (#132749) 2025-03-28 15:54:53 +00:00
Kazu Hirata
673f4705a8
[llvm] Use *Set::insert_range (NFC) (#133353)
We can use *Set::insert_range to collapse:

  for (auto Elem : Range)
    Set.insert(E.first);

down to:

  Set.insert_range(llvm::make_first_range(Range));

In some cases, we can further fold that into the set declaration.
2025-03-27 20:44:20 -07:00