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9 Commits

Author SHA1 Message Date
Craig Topper
a9253267a9 Prune includes in ARM target. 
llvm-svn: 204548
 2014-03-22 23:51:00 +00:00
Hao Liu
40b5ab8e5b [ARM]Fix an assertion failure in A15SDOptimizer about DPair reg class by treating DPair as QPR. 
llvm-svn: 204304
 2014-03-20 05:36:59 +00:00
Owen Anderson
16c6bf49b7 Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing 
operator* on the by-operand iterators to return a MachineOperand& rather than
a MachineInstr&.  At this point they almost behave like normal iterators!

Again, this requires making some existing loops more verbose, but should pave
the way for the big range-based for-loop cleanups in the future.

llvm-svn: 203865
 2014-03-13 23:12:04 +00:00
Craig Topper
6bc27bf359 [C++11] Add 'override' keyword to virtual methods that override their base class. 
llvm-svn: 203433
 2014-03-10 02:09:33 +00:00
Chandler Carruth
8a8cd2bab9 Re-sort all of the includes with ./utils/sort_includes.py so that 
subsequent changes are easier to review. About to fix some layering
issues, and wanted to separate out the necessary churn.

Also comment and sink the include of "Windows.h" in three .inc files to
match the usage in Memory.inc.

llvm-svn: 198685
 2014-01-07 11:48:04 +00:00
Alp Toker
f907b891da Correct word hyphenations 
This patch tries to avoid unrelated changes other than fixing a few
hyphen-related ambiguities and contractions in nearby lines.

llvm-svn: 196471
 2013-12-05 05:44:44 +00:00
Jim Grosbach
13654dd303 ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane. 
These instructions, such as vmul.f32, require the second source operand to
be in D0-D15 rather than the full D0-D31. When optimizing, make sure to
account for that by constraining the register class of a replacement virtual
register to be compatible with the virtual register(s) it's replacing.

I've been unsuccessful in creating a non-fragile regression test. This issue
was detected by the LLVM nightly test suite running on an A15 (Bullet).

PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093
llvm-svn: 189972
 2013-09-04 19:08:44 +00:00
Craig Topper
31ee5866de Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
llvm-svn: 185540
 2013-07-03 15:07:05 +00:00
Silviu Baranga
82dd6ac3bc Adding an A15 specific optimization pass for interactions between S/D/Q registers. The pass handles all the required transformations pre-regalloc. 
llvm-svn: 177169
 2013-03-15 18:28:25 +00:00