468286 Commits

Author SHA1 Message Date
Aiden Grossman
3336836dc2 [Docs][llvm-exegesis] Add documentation for memory annotations
Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D151039
2023-07-18 10:23:07 -07:00
Haojian Wu
21558c83db [clangd] Fix a build error for f4f6c229bde8f42721482469bd5a3d050d254d82 2023-07-18 19:20:06 +02:00
Craig Topper
0c055286b2 [RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.
This makes Zicond and XVentanaCondOps use the same code path.
The instructions have identical semantics.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155391
2023-07-18 10:18:02 -07:00
Quentin Colombet
9be8219f60 [mlir][Linalg] Add an interface to decompose complex ops
This patch adds an interface, named AggregatedOpInterface, that decomposes
complex operations into simpler ones.

For now, make the interface specific to Linalg because although the concept
is general, the way to materialize it needs some maturing.

Use that interface with the softmax operator.

Differential Revision: https://reviews.llvm.org/D154363
2023-07-18 19:06:36 +02:00
Craig Topper
d53d842d12 [RISCV][AArch64][IRGen] Add a special case to CodeGenFunction::EmitCall for scalable vector return being coerced to fixed vector.
Before falling back to CreateCoercedStore, detect a scalable vector
return being coerced to fixed vector. Handle it using a vector.extract
intrinsic without going through memory.

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D155495
2023-07-18 10:04:33 -07:00
eopXD
ca72457346 [RISCV] Add test coverage for peephole vmerge optimization of unmasked rvv instruction with a rounding mode (NFC)
No functional change intended.

Reviewed By: fakepaper56

Differential Revision: https://reviews.llvm.org/D155550
2023-07-18 10:03:58 -07:00
eopXD
eb89bf8d0d [RISCV] Do not use FPR registers for fastcc if zfh/f/d is not specified in the architecture
Resolves #63917.

Also lets the compiler check for available GPR before hitting the stack.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D155502
2023-07-18 10:03:04 -07:00
Arthur Eubanks
9983d276a1 [gn build] Manually port 2c651184 2023-07-18 09:53:35 -07:00
Craig Topper
cdee88a2e0 [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.
This allows TII isCopyInstrImpl to consider them copies.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155140
2023-07-18 09:49:23 -07:00
Craig Topper
7767297b58 [RISCV] Test for D155140. NFC
The vmv1r.v v8, v9 in the last block can be removed by late
copy propagation.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155527
2023-07-18 09:49:23 -07:00
Alan Zhao
fe0116aba8 [clang] Fix a crash when casting to an array type
In C++20, if Clang fails to perform constructor overload on a
RecordType, then Clang will try to perform parentesized aggregate
initialization. If that fails and the initialization was attempted as
part of a cast, then we should get the diagnostics from the failed
constructor overload attempt. However, we don't attempt constructor
overloading for arrays, so previously, if we try to diagnose an
overloaded cast for a parenthesized aggregate initialization of an
array, we crash. To fix this, we now exit tryDiagnoseOverloadedCast(...)
for failed parentesized list initialization if the destination type is
an array.

Fixes #63758

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D155523
2023-07-18 09:48:17 -07:00
Zhuojia Shen
b0093e13fc [AArch64] Merge LDRSWpre-LD[U]RSW pair into LDPSWpre
This patch optimizes a pair of LDRSWpre and LDRSWui (or LDURSWi)
instructions into a single LDPSWpre instruction.  This is a missing case
in D99272.

MIR test cases in D152564 are updated to verify the optimization.

Differential Revision: https://reviews.llvm.org/D152407
2023-07-18 09:46:47 -07:00
Zhuojia Shen
94f76004d5 [AArch64] Add tests for merging LDRSWpre-LDR pairs
This patch adds MIR test cases that test merging an LDRSWpre-LDR
instruction pair into an LDPSWpre instruction.  This optimization is
currently missing and will be added a subsequent patch (D152407), so all
test cases are no merge for now.

Differential Revision: https://reviews.llvm.org/D152564
2023-07-18 09:46:46 -07:00
Alexander Batashev
17508cbcc6 [NFC] Fix builds on recent GCC with C++20 enabled
The following pattern fails on recent GCC versions with -std=c++20 flag passed
and succeeds with -std=c++17. Such behavior is not observed on Clang 16.0.

```c++
template <typename T>
struct Foo {
    Foo<T>(int a) {}
};
```

This patch removes template parameter from constructor in two occurences to
make the following command complete successfully:
bazel build -c fastbuild --cxxopt=-std=c++20 --host_cxxopt=-std=c++20 @llvm-project//llvm/...

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D154782
2023-07-18 19:44:06 +03:00
Joseph Huber
e6b98b7eff [Clangd] Fix ambiguous use of 'Range'
Summary:
The changes in D155173 caused build failures on some configruations due
to the use of `Range` which conflicts with other definitions. Explicitly
use `clangd::Range`.
2023-07-18 11:41:24 -05:00
Joseph Huber
05abcc5792 [libc] Treat the locks array as a bitfield
Currently we keep an internal buffer of device memory that is used to
indicate ownership of a port. Since we only use this as a single bit we
can simply turn this into a bitfield. I did this manually rather than
having a separate type as we need very special handling of the masks
used to interact with the locks.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D155511
2023-07-18 11:34:21 -05:00
Simon Pilgrim
3ad4f92f83 [DAG] More aggressively (extract_vector_elt (build_vector x, y), c) iff element is zero constant
We currently don't extract vector elements from multi-use build vectors unless TLI.aggressivelyPreferBuildVectorSources accepts them, which seems a little extreme for constant build vectors (especially as under some cases ComputeKnownBits will indirectly extract the data for us).

This is causing a few regressions in some upcoming SimplifyDemandedBits work I'm looking at, all of which just need to know that the element is zero, so I've tweaked the fold to accept zero elements as well, which will typically fold very easily.

Differential Revision: https://reviews.llvm.org/D155582
2023-07-18 17:31:34 +01:00
Simon Pilgrim
b8bda50932 [Sparc] Regenerate float-constants.ll test checks 2023-07-18 17:31:34 +01:00
Rahul Kayaith
67a910bbff [mlir][python] Remove PythonAttr mapping functionality
This functionality has been replaced by TypeCasters (see D151840)

depends on D154468

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D154469
2023-07-18 12:21:28 -04:00
Dinar Temirbulatov
fe22b9050c [AArch64] Regenerate a couple of vector-shuffle tests. NFC
As a request in https://reviews.llvm.org/D152205
2023-07-18 16:04:15 +00:00
Joseph Huber
8759f1b030 Revert "[libc] Default the GPU build to the default memory utilities"
This reverts commit eca8b54a5f76c65a055bac05556b70c2a0ec63a1.

Another user reverted the patch this was based on leaving this one in a
broken state.
2023-07-18 11:01:38 -05:00
Slava Zakharin
daa8734233 [flang][hlfir] Support polymorphic hlfir.expr values.
This patch sets 'polymorphic' attribute of hlfir::ExprType when
the value is created from a polymorphic entity.
Memoization of such ExprType involves creating a mutable descriptor
on the stack, which is initialized (as a null box) and passed to
AllocatableApplyMold with the mold being the entity from which
the ExprType value is being created.

This patch fixes "creating polymorphic temporary" TODO and also
several cases of "'fir.convert' op invalid type conversion" error.

Reviewed By: tblah

Differential Revision: https://reviews.llvm.org/D155541
2023-07-18 09:00:26 -07:00
Joseph Huber
eca8b54a5f [libc] Default the GPU build to the default memory utilities
A previous patch made this cause an error on the GPU. We have not yet
dedicated time towards an optimial implementaiton there but we do not
want it to cause an error. We simply use the fallback routines.

Differential Revision: https://reviews.llvm.org/D155615
2023-07-18 10:49:51 -05:00
Jens Carl
37937b8a04 [clang-tidy][NFC] Update path of main translation unit
The forcing of the linker for a new module was moved from file
clang-tidy/tools/ClangTidyModule.cpp to
clang-tidy/ClangTidyForceLinker.h.

Reviewed By: PiotrZSL

Differential Revision: https://reviews.llvm.org/D76477
2023-07-18 15:49:01 +00:00
Jon Chesterfield
f717c2d4f2 Revert "[libc][memfunctions] Explicit error when platform in not supported"
Broke amdgpu libc bot

This reverts commit a39c951730aa92894e27da038e834229d4613db1.
2023-07-18 16:41:47 +01:00
Mark de Wever
ab0d757bcf [libc++][chrono] Fixes month inc and dec operations.
The operator++, operator++(int), operator--, and operator--(int) need to
change the month to a valid value. The wording is specified in terms of
  operator+(const month& x, const months& y) noexcept;
which has the correct behavior. The aforementioned operators instead
used ++/-- on the internal value direction, resulting in incorrect
behaviour.

As a drive-by improve the unit tests:
- use the typical constexpr test method
- test whether the month is valid after the operations
- format the tests

Fixes: https://llvm.org/PR63912

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D155504
2023-07-18 17:32:11 +02:00
Haojian Wu
f4f6c229bd [clangd] Refine the workflow for diagnostic Fixits.
- No longer store the diagnostic fixits in the clangdLSPServer
- When propagating the fixit via the code action, we use the Diag
  information stored in the ParsedAST (in clangdServer.cpp)

Differential Revision: https://reviews.llvm.org/D155173
2023-07-18 17:25:08 +02:00
Martin Storsjö
793a349e6f Revert "[AArch64] Fix an immediate out of range for large realignments on Windows"
This reverts commit b1d0bc0f4395c69097bc11b6ba8f821f621272a9.

Builds with expensive checks show that 'sp' isn't a valid register
in ADDXrr - an object file built without exprnsive checks enabled
disassembles as "add x15, xzr, x16", instead of the intended
"add x15, sp, x16".
2023-07-18 18:21:23 +03:00
Razvan Lupusoru
7496177d98 [openacc] Add dialect definition for acc declare
A declare directive is used to specify the creation of a visible device
copy of a variable for the duration of the implicit data region as it
relates to the scope in which the variable is declared.

In order to support this, the following new operations were added:
1) `acc.global_ctor` and `acc.global_dtor`. These are used whenever the
declare directive applies to a global.
2) `acc.declare_enter` and `acc.declare_exit`. These operations are
modeled similarly to `acc.enter_data` and `acc.exit_data`. The reason
they are not modeled like `acc.data` is so that these operations can be
used both for globals and regions like functions.
3) `acc.declare_device_resident` and `acc.declare_link`. These
operations are modeled in a manner consistent with previously defined
data entry operation model.

The `acc.getdeviceptr` was generalized so that it can be used with
acc.declare_exit.

Reviewed By: clementval, vzakhari

Differential Revision: https://reviews.llvm.org/D155322
2023-07-18 08:11:06 -07:00
Markus Böck
cde72af3db [mlir][LLVM] Append call ops alias scopes to inlined operations
Currently when inlining, any alias scope information previously attached to the call op is lost. This leads to a loss of information that could be used by alias analysis to determine that two memory access operations do not alias.

This patch fixes this issue by also taking any alias scopes of the call operation into account. These can then simply be appended onto any inlined operations.

This is analogous to the following code in LLVM: 1768c4597e/llvm/lib/Transforms/Utils/InlineFunction.cpp (L940)

Differential Revision: https://reviews.llvm.org/D155595
2023-07-18 16:26:17 +02:00
Ingo Müller
ef240e942a [mlir][transform][bufferization][python] Add .td file for bindings.
Reviewed By: springerm, ftynse

Differential Revision: https://reviews.llvm.org/D155564
2023-07-18 14:16:37 +00:00
Adrian Kuegel
7da6e0af1d [mlir][Bazel] Add missing dependency. 2023-07-18 16:10:48 +02:00
Adrian Kuegel
107a7d1f05 [mlir][Bazel] Add VectorToArmSME target. 2023-07-18 16:02:15 +02:00
Guillaume Chatelet
a39c951730 [libc][memfunctions] Explicit error when platform in not supported
Reviewed By: gchatelet

Differential Revision: https://reviews.llvm.org/D155597
2023-07-18 13:53:03 +00:00
Adrian Kuegel
7bde09cc24 [mlir][Bazel] Add missing dependency. 2023-07-18 15:51:49 +02:00
iambrj
3dd9931c0f [MLIR][Presburger] Implement domain and range restriction for PresburgerRelation
This patch implements domain and range restriction for PresburgerRelation

Reviewed By: Groverkss

Differential Revision: https://reviews.llvm.org/D154798
2023-07-18 19:12:12 +05:30
Martin Braenne
6236bf5341 [clang][dataflow] Strengthen flow condition assertions.
Instead of asserting merely that the flow condition doesn't imply that a variable is true, make the stronger assertion that the flow condition implies that the variable is false.

Reviewed By: ymandel, xazax.hun

Differential Revision: https://reviews.llvm.org/D155067
2023-07-18 13:41:43 +00:00
Paweł Bylica
7324535984
[clang][NFC] Fix typos in sema builtins test 2023-07-18 15:40:28 +02:00
Christoph Stiller
1768c4597e [MCA] Document behaviour of ResourceRef
Differential Revision: https://reviews.llvm.org/D155347
2023-07-18 14:09:21 +01:00
Alexey Bataev
83ba148a8a [SLP]Include cost of the reshuffling for same nodes with resizing.
Need to account reshuffling, required for the reused elements in the
buildvector nodes, which are copies (perfect match) of other nodes, but
include reused elements.

Differential Revision: https://reviews.llvm.org/D149966
2023-07-18 06:05:15 -07:00
John Brawn
343e204a52 [ARM] Replace TransferImpOps with copyImplicitOps
In most places where TransferImpOps is currently used we just have one
machine instruction, so it's doing the same thing as copyImplicitOps
anyway. In those cases where we have more than one machine
instruction the destination is written to in each instruction so any
implicit defs should appear on all of them (and we shouldn't see any
implicit refs as these pseudo-instruction don't have any register
inputs), meaning the current use of TransferImpOps is incorrect and
we should be using copyImplicitOps on all of the generated
instructions.

Differential Revision: https://reviews.llvm.org/D155301
2023-07-18 14:01:04 +01:00
wanglei
46aec7bc09 [LoongArch][NFC] Revise instruction format to match lsx and lasx styles
Replace lengthy `0b...` binary form with a unified 32-bit hexadecimal
 representation for opcode.  This reduces complexity when dealing with
 opcode discontinuities.
2023-07-18 20:58:34 +08:00
Martin Storsjö
b1d0bc0f43 [AArch64] Fix an immediate out of range for large realignments on Windows
Also add a missing FrameSetup flag on the existing add instruction.

This fixes https://github.com/llvm/llvm-project/issues/63701.

Differential Revision: https://reviews.llvm.org/D155447
2023-07-18 15:56:36 +03:00
Luke Lau
5eb7191421 [RISCV] Add VP patterns for vandn.[vv,vx]
This builds upon D155433

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155434
2023-07-18 13:53:17 +01:00
Luke Lau
26ff4c6745 [RISCV] Add SDNode patterns for vandn.[vv,vx]
Unfortunately we can't use the standard splat_vector and vnot PatFrags because
they are preprocessed to vmv.v.x's, so we need to define helpers to catch
those. We can't use SplatPat either because we need to nest another fragment
inside of it.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D155433
2023-07-18 13:53:14 +01:00
Matthias Springer
db393288ff [mlir][NVGPU][transform] Add create_async_groups transform op
This transform looks for suitable vector transfers from global memory to shared memory and converts them to async device copies.

Differential Revision: https://reviews.llvm.org/D155569
2023-07-18 14:36:41 +02:00
Guillaume Chatelet
23dcdbfba7 [libc][NFC] Split memmove implementations per platform
This is a follow up on D154800 and D154770 to make the code structure more principled and avoid too many nested #ifdef/#endif.

Reviewed By: courbet

Differential Revision: https://reviews.llvm.org/D155515
2023-07-18 12:20:23 +00:00
Jie Fu
30d11e5ef9 [Flang] Remove unused variable 'converter' in genCustomIntrinsicRefCore
/data/workspace/llvm-project/flang/lib/Lower/ConvertCall.cpp:1281:9: error: unused variable 'converter' [-Werror,-Wunused-variable]
  auto &converter = callContext.converter;
        ^
1 error generated.
2023-07-18 20:17:18 +08:00
Nikita Popov
eadbc4b004 [Constants] Use getGEPReturnType() (NFC)
This reimplements essentially the same logic.
2023-07-18 14:11:38 +02:00
dingfei
c24f0f9bd6 [NFC][clang-extdef-mapping] fix test failure on unsupported targets
ms-stlye asm block is not supported on targets like arm/hexagon.
Specify a working target as POC.

Introduced by https://reviews.llvm.org/D154983

Differential Revision: https://reviews.llvm.org/D155576
2023-07-18 19:56:50 +08:00