After changes in #109651.
Warning, treated as error:
/home/davspi01/work/open_source/llvm-project/llvm/docs/RISCVUsage.rst::Anonymous hyperlink mismatch: 1 references but 0 targets.
In typical RST fashion, all that was missing was a space between
the last word and the opening `<` of the link.
These are no longer experimental after
051054e6f74303bc880221e88671745f363964cc. I left the section because we
will be adding intrinsics for Zvkgs and Zvbc32e.
As discussed at the last sync-up call, mark Zacas as experimental until
this ABI issue is resolved
<https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>.
Don't return Zacas in getHostCPUFeatures (leaving a TODO there) as even if requesting detection of "native" features, the user likely doesn't want to automatically opt in to experimental codegen.
Both of them are ratified now.
https://wiki.riscv.org/display/HOME/Ratified+Extensions
This patch does not set them to non-experimental, since Zicfilp lacks
lld support and Zicfiss also lacks compiler-rt/libunwind support.
This extension consists of 8 additional 16-bit compressed forms for
existing standard load/store opcodes.
These opcodes are found in some RISC-V microcontrollers from WCH /
Nanjing Qinheng Microelectronics.
As discussed in the Discourse forums, this uses incompatible extension
and opcode names vs the vendor binary toolchain. The chosen names
instead follow the conventions for other vendor extensions listed on the
"riscv-non-isa" project.
This was reverted in f985a8826bfa4ca3d23e654185de35e30ea6dc79. Since that,
the default WMO lowering has moved to A67 compatible, the ABI attribute
emission has landed (off by default), and the LLD change to merge said
attributes have landed. Our ztso lowering is believed to also be A67
compatible, and no known issues remain.
Original commit message:
Ztso 1.0 was ratified in January 2023.
Documentation:
https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
The previous version of the document did not prefix the intrinsic names
with `__riscv_`. That has been corrected now. We have always implemented
the intrinsics with the `__riscv_` prefix so now the documentation
matches our implementation.
The document is now labeled as 1.1, but I have not changed the extension
version in the compiler since it was only changing the intrinsic names.
These extensions had their version number bumped and still experimental
(under public review). I didn't see anything in the [commit
history](https://github.com/riscv/riscv-j-extension/commits/master/)
since #79929 that would warrant a change to the implementation of
pointer masking in the compiler.
Specification link:
https://github.com/riscv/riscv-isa-manual/blob/main/src/indirect-csr.adoc
Some CSRs (`*ireg` and `*iselect`) in Smcsrind/Sscsrind extensions are
originally defined as part of the Smaia/Ssaia extensions and are already
supported in LLVM. The missing CSRs (`*ireg2` to `*ireg6` for `m`, `s`,
and `vs`) are added in this PR.
It seems that we have `B` extension again:
https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
Though it hasn't been ratified, I set its version to `1.0`.
These were in LLVM 17 but removed from LLVM 18 due to an incorrect
extension name being used.
This restores them with new extension names that match SiFive's
downstream compiler. The extension name has been used internally for
some time. It uses XSiFive instead of XSf like the newer extensions.
`cease` did not have an internal extension name so its using the `XSf`
convention.
The spec for the instructions is here
https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf
though the extension name is not listed.
Column width in the extension printing had to be changed to accommodate
a longer extension name.
This patch implements the codegen support of zabha (Byte and Halfword
Atomic Memory Operations) v1.0-rc1 extension.
See also https://github.com/riscv/riscv-zabha/blob/v1.0-rc1/zabha.adoc.
---------
Co-authored-by: Craig Topper <craig.topper@sifive.com>
Using a single underscore creates a reference target. If the target
name has the same name as another link, we get a "Duplicate target name"
warning. This is currently happening for Ssqosid.
Using __ prevents this. I've converted all links so no one trips over
this in the future.
One link was missing any underscores so wasn't a link at all in the
generated html.
This patch implements the v0.8.1 specification. This patch reports
version 0.8 in llvm since `RISCVISAInfo::ExtensionVersion` only has a
`Major` and `Minor` version number. This patch includes includes support
of the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make
up RISC-V pointer masking.
All of these extensions require emitting attribute containing correct
`march` string.
`Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a 2-bit WARL field (PMM).
The extension does not specify how PMM is set, and therefore this patch
does not need to address this. One example of how it *could* be set is
using the Zicsr instructions to update the PMM bits of the described
registers.
The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
This is a good portion of the extensions mentioned in the RVA23 profile
here
https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc
I don't believe these add any new CSRs. Sstc does add new CSRs, but we
already added them without the extension name a while back.
I tried to keep the descriptions in RISCVFeatures.td fairly short since
the strings show up in `-print-supported-extensions`.
The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tuning that could be done about when to select Zicond or not, there
are no known correctness issues. Therefore, we should mark support as
non-experimental.
