David Woodhouse
32da3c8f3b
[x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
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It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.
Hm, perhaps we do need an AdSize16 bit after all?
llvm-svn: 198759
2014-01-08 12:58:24 +00:00
Craig Topper
3321c99a06
Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
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llvm-svn: 198284
2014-01-01 21:52:57 +00:00
Elena Demikhovsky
de3f751baf
AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp
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Printing rounding control.
Enncoding for EVEX_RC (rounding control).
llvm-svn: 198277
2014-01-01 15:12:34 +00:00
Elena Demikhovsky
371e363833
AVX-512: decoder for AVX-512, made by Alexey Bader.
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llvm-svn: 198013
2013-12-25 11:40:51 +00:00
Elena Demikhovsky
dacddb0bab
AVX-512: added VPCONFLICT instruction and intrinsics,
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added EVEX_KZ to tablegen
llvm-svn: 193959
2013-11-03 13:46:31 +00:00
Craig Topper
9e3e38ae3f
Add XOP disassembler support. Fixes PR13933.
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llvm-svn: 191874
2013-10-03 05:17:48 +00:00
Craig Topper
009de6015f
Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K.
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llvm-svn: 191652
2013-09-30 06:23:19 +00:00
Craig Topper
ed59dd34fd
Various x86 disassembler fixes.
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Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
llvm-svn: 191649
2013-09-30 02:46:36 +00:00
Elena Demikhovsky
003e7d73b9
Added encoding prefixes for KNL instructions (EVEX).
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Added 512-bit operands printing.
Added instruction formats for KNL instructions.
llvm-svn: 187324
2013-07-28 08:28:38 +00:00
Chandler Carruth
91d19d8e93
Sort the #include lines for utils/...
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I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.
llvm-svn: 169251
2012-12-04 10:37:14 +00:00
Craig Topper
963305b450
Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren.
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llvm-svn: 163774
2012-09-13 05:45:42 +00:00
Craig Topper
8702c5b7c0
Change unsigned to a uint16_t in static disassembler tables to reduce the table size.
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llvm-svn: 163594
2012-09-11 04:19:21 +00:00
Craig Topper
b8aec08819
Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.
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llvm-svn: 161101
2012-08-01 07:39:18 +00:00
Craig Topper
9caea12bd8
Use uint8_t to store the InstructionContext table. Saves 768 bytes of static data.
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llvm-svn: 161034
2012-07-31 06:15:39 +00:00
Craig Topper
6f142746e7
Tidy up. Move for loop index declarations into for statements. Use unsigned instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent.
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llvm-svn: 161033
2012-07-31 06:02:05 +00:00
Craig Topper
b61024cfcc
Tidy up function argument formatting.
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llvm-svn: 161032
2012-07-31 05:42:02 +00:00
Craig Topper
0c4253fe29
Remove trailing whitespace
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llvm-svn: 161030
2012-07-31 05:27:01 +00:00
Craig Topper
6dedbae429
Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o
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llvm-svn: 151995
2012-03-04 02:16:41 +00:00
Craig Topper
6491c8020e
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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llvm-svn: 151510
2012-02-27 01:54:29 +00:00
Ahmed Charles
636a3d618c
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
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llvm-svn: 150918
2012-02-19 11:37:01 +00:00
Benjamin Kramer
478e8de8ef
Reuse the enum names from X86Desc in the X86Disassembler.
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This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.
llvm-svn: 150303
2012-02-11 14:50:54 +00:00
Craig Topper
a0cd970b81
More tweaks to get the size of the X86 disassembler tables down.
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llvm-svn: 150167
2012-02-09 08:58:07 +00:00
Craig Topper
487e744f66
Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953.
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llvm-svn: 150161
2012-02-09 07:45:30 +00:00
David Blaikie
b48ed1a4cb
Remove unreachable code. (replace with llvm_unreachable to help GCC where necessary)
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llvm-svn: 148284
2012-01-17 04:43:56 +00:00
Craig Topper
f01f1b5cb9
More AVX2 instructions and their intrinsics.
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llvm-svn: 143895
2011-11-06 23:04:08 +00:00
Craig Topper
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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llvm-svn: 141642
2011-10-11 04:34:23 +00:00
Craig Topper
5aebebe18d
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
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llvm-svn: 141353
2011-10-07 05:35:38 +00:00
Craig Topper
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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llvm-svn: 141065
2011-10-04 06:30:42 +00:00
Craig Topper
56ff34f7c5
Fix typo in r140954.
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llvm-svn: 140962
2011-10-02 04:54:26 +00:00
Craig Topper
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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llvm-svn: 140954
2011-10-01 19:54:56 +00:00
Peter Collingbourne
84c287e33c
Move TableGen's parser and entry point into a library
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This is the first step towards splitting LLVM and Clang's tblgen executables.
llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Craig Topper
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
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llvm-svn: 140370
2011-09-23 06:57:25 +00:00
Craig Topper
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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llvm-svn: 139484
2011-09-11 20:23:20 +00:00
Craig Topper
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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llvm-svn: 138997
2011-09-02 04:17:54 +00:00
Craig Topper
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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llvm-svn: 138552
2011-08-25 07:42:00 +00:00
Joerg Sonnenberger
fc4789da4a
Add support for the VIA PadLock instructions.
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llvm-svn: 128826
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
c94780c539
Use array_lengthof
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llvm-svn: 128823
2011-04-04 16:25:38 +00:00
Joerg Sonnenberger
fb3bce155e
Change loops to derive the number of tables automatically
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llvm-svn: 128818
2011-04-04 14:42:22 +00:00
Sean Callanan
c3fd523731
X86 table-generator and disassembler support for the AVX
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instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
2011-03-15 01:23:15 +00:00
Benjamin Kramer
34402c4fe4
Constify another 2 disassembler tables.
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llvm-svn: 117208
2010-10-23 09:28:42 +00:00
Benjamin Kramer
de0a4fbf3b
Make the disassembler tables const so they end up in read-only memory.
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llvm-svn: 117206
2010-10-23 09:10:44 +00:00
Benjamin Kramer
9192e7ab12
Make some symbols static, move classes into anonymous namespaces.
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llvm-svn: 117111
2010-10-22 17:35:07 +00:00
Dan Gohman
b29cda9b3c
Fix a bunch of namespace polution.
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llvm-svn: 101376
2010-04-15 17:08:50 +00:00
Daniel Dunbar
c7dccd8ad2
Suppress compiler warning.
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llvm-svn: 91959
2009-12-23 00:45:10 +00:00
Nuno Lopes
91b866a163
fix build and while at it remove a redudant include
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llvm-svn: 91774
2009-12-19 11:52:18 +00:00
Daniel Dunbar
3a821f7f0c
More bzero -> memset that I missed.
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llvm-svn: 91757
2009-12-19 04:16:57 +00:00
Sean Callanan
04cc307edd
Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
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incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
llvm-svn: 91749
2009-12-19 02:59:52 +00:00