17 Commits

Author SHA1 Message Date
Scott Michel
7d5eaec6dd Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:

- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
  esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
  rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
  is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
  compiles and generates the right code. More work still needs to be done.

llvm-svn: 47532
2008-02-23 18:41:37 +00:00
Evan Cheng
3b3286d4bc It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Scott Michel
bb713ae0c7 More cleanups for CellSPU:
- Expand tabs... (poss 80-col violations, will get them later...)
- Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single
  function, simplifying maintenance. Also reduced custom instruction
  generation for SPUvecinsert/INSERT_MASK.

llvm-svn: 46544
2008-01-30 02:55:46 +00:00
Chris Lattner
f0f438a517 remove MachineOpCode typedef.
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Owen Anderson
2a3be7bb6c Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Owen Anderson
eee14601b1 Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner
25568e4cef Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson
7a73ae9a86 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner
a5bb370aa4 Add new shorter predicates for testing machine operands for various types:
e.g. MO.isMBB() instead of MO.isMachineBasicBlock().  I don't plan on 
switching everything over, so new clients should just start using the 
shorter names.

Remove old long accessors, switching everything over to use the short
accessor: getMachineBasicBlock() -> getMBB(), 
getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc.

llvm-svn: 45464
2007-12-30 23:10:15 +00:00
Chris Lattner
5c4637816e Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm
llvm-svn: 45453
2007-12-30 20:49:49 +00:00
Chris Lattner
f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Scott Michel
5f1470f03a More working CellSPU tests:
- vec_const.ll: Vector constant loads
- immed64.ll: i64, f64 constant loads

llvm-svn: 45242
2007-12-20 00:44:13 +00:00
Scott Michel
098c113bc8 Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll
(vector insertions)

llvm-svn: 45216
2007-12-19 20:15:47 +00:00
Scott Michel
9b834469e0 Add new immed16.ll test case, fix CellSPU errata to make test case work.
llvm-svn: 45196
2007-12-19 07:35:06 +00:00
Scott Michel
c5cccb9e60 - Restore some i8 functionality in CellSPU
- New test case: nand.ll

llvm-svn: 45130
2007-12-17 22:32:34 +00:00
Scott Michel
d1b5b9f68c Updated source file headers to llvm coding standard.
llvm-svn: 44597
2007-12-05 01:40:25 +00:00
Scott Michel
dfe09ed085 More files in the CellSPU drop...
llvm-svn: 44584
2007-12-04 22:35:58 +00:00