mirrors/llvm-project
0
0
Fork 0
mirror of https://github.com/llvm/llvm-project.git synced 2025-05-01 16:06:07 +00:00
Code Issues Projects Releases Wiki Activity
177,185 Commits 1,258 Branches 288 Tags
Commit Graph

164 Commits

Author SHA1 Message Date
Aaron Ballman
3c81e46b57 Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended. 
llvm-svn: 211783
 2014-06-26 13:45:47 +00:00
Matt Arsenault
c6f8fdb4e5 R600: Fix vector FMA 
llvm-svn: 211757
 2014-06-26 01:28:05 +00:00
Tom Stellard
9b3816b5ee R600: Promote i64 stores to v2i32 
Now we need only one 64-bit pattern for stores.

llvm-svn: 211643
 2014-06-24 23:33:04 +00:00
Matt Arsenault
257d48d22c R600: Fix inconsistency in rsq instructions. 
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

llvm-svn: 211637
 2014-06-24 22:13:39 +00:00
Matt Arsenault
d40b970616 R600: Remove DIV_INF 
This corresponded to an amdil instruction which there is
a 2 instruction equivalent for.

llvm-svn: 211616
 2014-06-24 17:42:16 +00:00
Matt Arsenault
f2b0aebb8a R600/SI: Fix div_scale intrinsic. 
The operand that must match one of the others does matter,
and implement selecting for it.

llvm-svn: 211523
 2014-06-23 18:28:28 +00:00
Matt Arsenault
1d555c4e91 R600: Remove AMDILISelLowering 
llvm-svn: 211519
 2014-06-23 18:00:55 +00:00
Matt Arsenault
d5f91fd883 R600: Select is not expensive. 
llvm-svn: 211518
 2014-06-23 18:00:52 +00:00
Matt Arsenault
c4d3d3a16e R600: Move add/sub with overflow out of AMDILISelLowering 
Add more tests for these.

llvm-svn: 211517
 2014-06-23 18:00:49 +00:00
Matt Arsenault
e54e1c3a21 R600: Move more out of AMDILISelLowering 
llvm-svn: 211516
 2014-06-23 18:00:44 +00:00
Matt Arsenault
b8b5153935 R600/SI: Handle i64 sub. 
We can handle it the same way as add

llvm-svn: 211514
 2014-06-23 18:00:38 +00:00
Matt Arsenault
c791f39912 R600: Rename AMDIL file 
llvm-svn: 211512
 2014-06-23 18:00:31 +00:00
Jan Vesely
343cd6f056 R600: Use LowerSDIVREM for i64 node replace 
v2: move div/rem node replacement to R600ISelLowering
    make lowerSDIVREM protected

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211478
 2014-06-22 21:43:01 +00:00
Jan Vesely
109efdff6a R600: Implement custom SDIVREM. 
Instead of separate SDIV/SREM. SDIV used UDIV which in turn used UDIVREM anyway.
SREM used SDIV(UDIV->UDIVREM)+MUL+SUB, using UDIVREM directly is more efficient.

v2: Don't use all caps names

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211477
 2014-06-22 21:43:00 +00:00
Tom Stellard
9c603ebca4 R600/SI: Add a pattern for f32 ftrunc 
llvm-svn: 211377
 2014-06-20 17:06:09 +00:00
Tom Stellard
a79e9f0f6d R600: Expand vector flog2 
llvm-svn: 211376
 2014-06-20 17:06:07 +00:00
Tom Stellard
5222a88653 R600: Expand vector fexp2 
llvm-svn: 211375
 2014-06-20 17:06:05 +00:00
Matt Arsenault
a0050b0961 R600/SI: Add intrinsics for various math instructions. 
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

llvm-svn: 211247
 2014-06-19 01:19:19 +00:00
Matt Arsenault
2b0fa433a0 Use stdint macros for specifying size of constants 
llvm-svn: 211231
 2014-06-18 22:11:03 +00:00
Matt Arsenault
692bd5ec2f R600: Handle fnearbyint 
The difference from rint isn't really relevant here,
so treat them as equivalent. OpenCL doesn't have nearbyint,
so this is sort of pointless other than for completeness.

llvm-svn: 211229
 2014-06-18 22:03:45 +00:00
Matt Arsenault
b55c68f171 Use LL suffix for literal that should be 64-bits. 
This hopefully fixes Windows

llvm-svn: 211225
 2014-06-18 21:40:43 +00:00
Jan Vesely
85f0dbce5c R600: Expand vector fceil 
Move fp64 fceil tests to fceil64.ll

v2: rebase

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 211194
 2014-06-18 17:57:29 +00:00
Matt Arsenault
d22626f6bb Work around ridiculous warning. 
Apparently C++ doesn't really have hex floating point constants.

llvm-svn: 211192
 2014-06-18 17:45:58 +00:00
Matt Arsenault
43160e7af2 R600/SI: Add intrinsics for brev instructions 
llvm-svn: 211187
 2014-06-18 17:13:57 +00:00
Matt Arsenault
4601093267 R600: Implement f64 ftrunc, ffloor and fceil. 
CI has instructions for these, so this fixes them for older hardware.

llvm-svn: 211183
 2014-06-18 17:05:30 +00:00
Matt Arsenault
e8208ec95b R600: Custom lower f64 frint for pre-CI 
llvm-svn: 211182
 2014-06-18 17:05:26 +00:00
Matt Arsenault
8579601050 R600/SI: Match ctlz_zero_undef 
llvm-svn: 211115
 2014-06-17 17:36:24 +00:00
Tom Stellard
880a80ad07 R600: Use LDS and vectors for private memory 
llvm-svn: 211110
 2014-06-17 16:53:14 +00:00
Tom Stellard
aad4659470 SelectionDAG: Expand i64 = FP_TO_SINT i32 
llvm-svn: 211108
 2014-06-17 16:53:07 +00:00
Matt Arsenault
2a60de548a Fix copy paste error 
llvm-svn: 211003
 2014-06-15 21:22:52 +00:00
Matt Arsenault
717c1d0319 R600: Remove a few more things from AMDILISelLowering 
Try to keep all the setOperationActions for integer ops
together.

llvm-svn: 211001
 2014-06-15 21:08:58 +00:00
Matt Arsenault
b5dff9ab50 R600: Fix assert on vector sdiv 
llvm-svn: 211000
 2014-06-15 21:08:54 +00:00
Matt Arsenault
14d4645e46 R600: Move / cleanup more leftover AMDIL stuff. 
llvm-svn: 210998
 2014-06-15 20:23:38 +00:00
Matt Arsenault
1578aa78d4 R600: Move division custom lowering out of AMDILISelLowering 
llvm-svn: 210997
 2014-06-15 20:08:02 +00:00
Matt Arsenault
cf9a9a148e R600: Report that integer division is expensive. 
Divides by weird constants now emit much better code.

llvm-svn: 210995
 2014-06-15 19:48:16 +00:00
Matt Arsenault
e682a19a1c R600: Fix asserts related to constant initializers 
This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.

An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.

llvm-svn: 210967
 2014-06-14 04:26:05 +00:00
Matt Arsenault
41aa27c96b R600: Use address space enum instead of value 
llvm-svn: 210966
 2014-06-14 04:26:01 +00:00
Matt Arsenault
fd8c24ede8 R600: Cleanup some old AMDIL stuff. 
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.

No functionality change.

llvm-svn: 210922
 2014-06-13 17:20:53 +00:00
Matt Arsenault
825fb0b094 R600/SI: Fix selection error on i64 rotl / rotr. 
Evergreen is still broken due to missing shl_parts.

llvm-svn: 210885
 2014-06-13 04:00:30 +00:00
Matt Arsenault
5d47d4ac7e R600: Mostly remove remaining AMDIL intrinsics. 
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
 2014-06-12 21:15:44 +00:00
Matt Arsenault
364a6747aa R600/SI: Use v_cvt_f32_ubyte* instructions 
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
 2014-06-11 17:50:44 +00:00
Rafael Espindola
ace0080a4a Try to fix the msvc build. 
llvm-svn: 210636
 2014-06-11 04:41:37 +00:00
Matt Arsenault
10da3b2516 Use cast instead of assert + dyn_cast 
llvm-svn: 210628
 2014-06-11 03:30:06 +00:00
Matt Arsenault
c9df794042 R600: Add helper functions. 
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
 2014-06-11 03:29:54 +00:00
Matt Arsenault
6042506b5c R600: Use BCNT_INT for evergreen 
llvm-svn: 210569
 2014-06-10 19:18:28 +00:00
Matt Arsenault
b5b5110b5c R600/SI: Use bcnt instruction for ctpop 
llvm-svn: 210567
 2014-06-10 19:18:21 +00:00
Matt Arsenault
6e43965fbc R600: Handle fcopysign 
llvm-svn: 210564
 2014-06-10 19:00:20 +00:00
Matt Arsenault
13ccc8f1bc R600: Fix selection failure for vector bswap 
llvm-svn: 210475
 2014-06-09 16:20:25 +00:00
Matt Arsenault
616a8e42b1 R600: Set all float vector expands in the same place 
llvm-svn: 209988
 2014-06-01 07:38:21 +00:00
Matt Arsenault
05e96f4444 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

llvm-svn: 209462
 2014-05-22 18:09:12 +00:00