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94 Commits

Author SHA1 Message Date
Yeting Kuo
3dc0638cfc
[RISCV] Add MC layer support for Zicfiss. (#66043) 
The patch adds the instructions in Zicfiss extension. Zicfiss extension
is to support shadow stack for control flow integrity. This patch is
based on version [0.3.1].

[0.3.1]: https://github.com/riscv/riscv-cfi/releases/tag/v0.3.1
 2023-12-30 15:40:20 +08:00
Craig Topper
6dc5ba4cca [RISCV] Remove XSfcie extension. 
This reverts 0d3eee33f262402562a1ff28106dbb2f59031bdb and
4c37d30e22ae655394c8b3a7e292c06d393b9b44.

XSfcie is not an official SiFive extension name. It stands for
SiFive Custom Instruction Extension, which is mentioned in the S76
manual, but then elsewhere in the manual says it is not supported
for S76.

LLVM had various instructions and CSRs listed as part of this
extension, but as far as SiFive is concerned, none of them are part
of it. There are no documented extension names for these instructions
and CSRs either externally or internally.

If these are important to LLVM users, I can facilitate creating
extension names for them and have them documented. For now I'm
removing everything.

Unfortunately, these instructions and CSRs are in LLVM 17 so this
is an incompatible change.
 2023-12-28 13:54:15 -08:00
Yeting Kuo
256bf56afa
[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061) 
he spimm operand is an immediate whose only 4-5th bit could be setted
and not based on rlist operand
 2023-12-27 09:11:34 +08:00
LiaoChunyu
71a7108ee9 [RISCV][MC] MC layer support for xcvmem and xcvelw extensions 
This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Several other extensions have been merged.
Spec:
https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst
Contributors: @CharKeaney, @jeremybennett, @lewis-revill, Nandni Jamnadas, @PaoloS, @simoncook, @xmj, @realqhc, @melonedo, @adeelahmad81299

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D158824
 2023-11-16 09:46:11 +08:00
Brandon Wu
74f38df1d1
[RISCV] Support Xsfvfnrclipxfqf extensions (#68297) 
FP32-to-int8 Ranged Clip Instructions

https://sifive.cdn.prismic.io/sifive/0aacff47-f530-43dc-8446-5caa2260ece0_xsfvfnrclipxfqf-spec.pdf
 2023-11-03 10:52:37 +08:00
Brandon Wu
945d2e6e60
[RISCV] Support Xsfvfwmaccqqq extensions (#68296) 
Bfloat16 Matrix Multiply Accumulate Instruction

https://sifive.cdn.prismic.io/sifive/c391d53e-ffcf-4091-82f6-c37bf3e883ed_xsfvfwmaccqqq-spec.pdf
 2023-11-03 10:08:26 +08:00
flyingcat
e6971e5a41
[RISCV][NFC] Simplify vector register decoding methods (#70423) 
Combine redundant 'if' statements and simplify 'switch' statements.
 2023-10-31 10:01:07 +08:00
Brandon Wu
d1985e3d1f
[RISCV] Support Xsfvqmaccdod and Xsfvqmaccqoq extensions (#68295) 
SiFive Int8 Matrix Multiplication Extensions Specification

https://sifive.cdn.prismic.io/sifive/c4f0e51d-4dd3-402a-98bc-1ffad6011259_int8-matmul-spec.pdf
 2023-10-20 11:16:20 +08:00
Jim Lin
f3c0eaeb2e [RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC. 
All of them have prefix 'X' in DecoderNamespace.
 2023-08-19 12:44:59 +08:00
Craig Topper
b4bb111b80 [RISCV] Rename XTHead DecoderNamespaces to match their extension names include the 'X'. NFC 
This is consistent with other vendor extensions.
 2023-07-30 12:09:03 -07:00
Craig Topper
0c7d897627 [RISCV] Rename DecoderNamespace for XCVsimd to be consistent with other XCV extensions. NFC 2023-07-30 12:00:46 -07:00
melonedo
afb9c04a5a [RISCV] Add support for XCVbi extension in CV32E40P 
Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj.

bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited.
e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in.
This commit removed the conflict marker and recommitted.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412
 2023-07-28 21:54:10 +08:00
melonedo
e4777dc4b9 Revert "[RISCV] Add support for XCVbi extension in CV32E40P" 
This reverts commit bf2ad26b4ff856aab9a62ad168e6bdefeedc374f as it
checked in merge conflict markers.
 2023-07-28 19:28:20 +08:00
melonedo
bf2ad26b4f [RISCV] Add support for XCVbi extension in CV32E40P 
Implement XCVbi intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154412
 2023-07-28 17:36:57 +08:00
melonedo
3c0604b224 [RISCV] Add support for XCVsimd extension in CV32E40P 
Implement XCVsimd intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @PaoloS, @simoncook, @xmj.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153721
 2023-07-28 16:52:32 +08:00
Qihan Cai
092e60a3fc [RISCV] Add support for XCValu extension in CV32E40P 
Implement XCValu intrinsics for CV32E40P according to the specification.

This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153748
 2023-07-28 11:37:31 +08:00
Garvit Gupta
4c37d30e22 [RISCV] Add support for custom instructions for Sifive S76. 
Support for below instruction is added
1. CFLUSH.D.L1
2. CDISCARD.D.L1
3. CEASE

Additionally, Zihintpause extension is added to sifive s76 for pause
instruction.

Spec - https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153370
 2023-06-26 11:36:00 -07:00
Qihan Cai
e219dd88d1 [RISCV] Add support for XCVmac extension in CV32E40P 
Implement XCVmac intrinsics for CV32E40P according to the specification.

This is the first commit of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

The patch-set aims at upstreaming the extensions on MC. The following will be on CodeGen, and the final patch-set will be on builtins if possible. The implemented version is on [0].

Contributors: @CharKeaney, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj

Spec: 62bec66b36/docs/source/instruction_set_extensions.rst

[0] https://github.com/openhwgroup/corev-llvm-project

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152821
 2023-06-21 23:08:49 +08:00
melonedo
c5a412dad5 [RISCV] Add support for XCVbitmanip extension in CV32E40P 
Implement XCVbitmanip intrinsics for CV32E40P according to the specification.

This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P.

Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj.

Spec: 62bec66b36/docs/source/instruction_set_extensions.rst

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D152915
 2023-06-19 21:16:07 +08:00
wangpc
92723d5a32 [RISCV][NFC] Simplify decoding code of disassembler 
The decoding parts are reduplicative, we add a macro to simplify
the code.

Reviewed By: craig.topper, kito-cheng

Differential Revision: https://reviews.llvm.org/D151309
 2023-05-25 15:24:41 +08:00
Craig Topper
8f43c3f49e [RISCV] Rework how implied SP operands work in the disassembler. NFC 
Previously we added the SP operands when an immediate operand was added
to certain opcodes.

This patch moves it to a post processing step using the information
in MCInstrDesc. This avoids an explicit opcode list in RISCVDisassembler.cpp.

In considered using a custom DecoderMethod, but the bit swizzling we
need to do for the immediates on these instructions made that
unattractive.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D149931
 2023-05-16 09:43:38 -07:00
WuXinlong
6b55e9117e [RISCV] Add MC support of RISCV zcmp Extension 
This patch add the instructions of zcmp extension.

Instructions in zcmp extension try to optimise `mv` inst and the prologue & epilogue in functions

co-author: @Scott Egerton, @ZirconLiu, @Lukacma, @Heda Chen, @luxufan, @heyiliang, @liaochunyu

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D132819
 2023-05-08 14:29:50 +08:00
Craig Topper
7b3b178c82 [RISCV] Add DecoderNamespace to Zcmt instructions. 
The Zcmt instructions overlap encoding space with some C extension
instructions. Isolate to a separate namespace.

Reviewed By: VincentWu

Differential Revision: https://reviews.llvm.org/D149891
 2023-05-05 10:08:43 -07:00
Craig Topper
d421c5f81a [RISCV] Directly create MCOperands from addImplySP in Disassembler. NFC 
Instead of passing a constant to DecodeGPRRegisterClass, just create
the X2 register directly.
 2023-05-04 22:18:33 -07:00
Nelson Chu
0b9a620b83 [RISCV] Support assembler and dis-assembler for VCIX extension. 
Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf

Differential Revision: https://reviews.llvm.org/D144530
 2023-04-09 20:41:01 -07:00
Craig Topper
29463612d2 [RISCV] Replace RISCV -> RISC-V in comments. NFC 
To be consistent with RISC-V branding guidelines
https://riscv.org/about/risc-v-branding-guidelines/
Think we should be using RISC-V where possible.

More patches will follow.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D146449
 2023-03-27 09:50:17 -07:00
Job Noorman
c39dd7c1db [RISCV][MC] Add support for RV64E 
Implement MC support for the recently ratified RV64E base instruction
set.

Differential Revision: https://reviews.llvm.org/D143570
 2023-03-23 12:32:25 +00:00
Philipp Tomsich
f68f04d07c [RISCV] Add vendor-defined XTheadCondMov (conditional move) extension 
The vendor-defined XTheadCondMov (somewhat related to the upcoming
Zicond and XVentanaCondOps) extension add conditional move
instructions with $rd being an input and an ouput instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=73442230966a22b3238b2074691a71d7b4ed914a

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144681
 2023-02-24 21:40:42 +01:00
Manolis Tsamis
7b79e8d455 [RISCV] Add vendor-defined XTheadFMemIdx (FP Indexed Memory Operations) extension 
The vendor-defined XTHeadFMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
for floating-point registers.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f511f80fa3fcaf6bcbe727fb902b8bd5ec8f9c20

Depends on D144249

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144647
 2023-02-24 00:35:37 +01:00
Manolis Tsamis
f6262201d8 [RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension 
The vendor-defined XTHeadMemIdx (no comparable standard extension exists
at the time of writing) extension adds indexed load/store instructions
as well as load/store and update register instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=27cfd142d0a7e378d19aa9a1278e2137f849b71b

Depends on D144002

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144249
 2023-02-24 00:17:58 +01:00
Manolis Tsamis
16a6cf6a99 [RISCV] Add vendor-defined XTheadSync (Multi-core synchronization) extension 
The vendor-defined XTheadSync (no comparable standard extension exists
at the time of writing) extension adds multi-core synchronization
instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=547c18d9bb95571261dbd17f4767194037eb82bd

Depends on D144496

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144501
 2023-02-22 11:15:40 +01:00
Manolis Tsamis
f5b484c56f [RISCV] Add vendor-defined XTheadCmo (Cache Management Operations) extension 
The vendor-defined XTHeadCmo (there are some similarities with the
Zicbom standard extension) extension adds cache management instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=a9ba8bc2d396fb8ae2b892f3bc6be8cdfe4b555c

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144496
 2023-02-22 10:57:48 +01:00
Manolis Tsamis
bbb58a2302 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension 
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D144002
 2023-02-21 12:21:49 +01:00
Craig Topper
34aff47521 [RISCV] Use MCSubtargetInfo::hasFeature where possible. NFC 
Rather than using operator[] on getFeatureBits we can use
hasFeature to shorten the code.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D144300
 2023-02-17 14:36:48 -08:00
Philipp Tomsich
16a66af0a0 Revert "[RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension" 
This reverts commit d2918544a7fc4b5443879fe12f32a712e6dfe325.
 2023-02-17 19:45:55 +01:00
Manolis Tsamis
d2918544a7 [RISCV] Add vendor-defined XTheadMemPair (two-GPR Memory Operations) extension 
The vendor-defined XTHeadMemPair (no comparable standard extension exists
at the time of writing) extension adds two-GPR load/store pair instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=6e17ae625570ff8f3c12c8765b8d45d4db8694bd

Depends on D143847

Differential Revision: https://reviews.llvm.org/D144002
 2023-02-17 19:45:22 +01:00
Manolis Tsamis
d4012bc43f [RISCV] Add vendor-defined XTheadMAC (multiply-accumulate) extension 
The vendor-defined XTHeadMAC (no comparable standard extension exists
at the time of writing) extension adds multiply accumulate instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for this
extension is available at:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=4041e11db3ec3611921d10150572a92689aa3154

Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143847
 2023-02-14 20:25:47 +01:00
Philipp Tomsich
fc02eeb24f [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension 
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143439
 2023-02-13 17:02:09 +01:00
Philipp Tomsich
04a2baf58f [RISCV] Add vendor-defined XTHeadBs (single-bit) extension 
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143036
 2023-02-13 16:28:26 +01:00
Philipp Tomsich
0bda199285 Revert "[RISCV] Add vendor-defined XTHeadBs (single-bit) extension" 
This reverts commit 656188ddc4075eb50260607b3497589873f373d2.
 2023-02-08 08:00:45 +01:00
Philipp Tomsich
b0c3132226 Revert "[RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension" 
This reverts commit 19a59099095b3cbc9846e5330de26fca0a44ccbe.
 2023-02-08 08:00:34 +01:00
Philipp Tomsich
19a5909909 [RISCV] Add vendor-defined XTheadBb (basic bit-manipulation) extension 
The vendor-defined XTHeadBb (predating the standard Zbb extension)
extension adds some bit-manipulation extensions with somewhat similar
semantics as some of the Zbb instructions.

It is supported by the C9xx cores (e.g., found in the wild in the
Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBb is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143036

Differential Revision: https://reviews.llvm.org/D143439
 2023-02-08 07:57:27 +01:00
Philipp Tomsich
656188ddc4 [RISCV] Add vendor-defined XTHeadBs (single-bit) extension 
The vendor-defined XTHeadBs (predating the standard Zbs extension)
extension adds a bit-test instruction (th.tst) with similar semantics
as bexti from Zbs.  It is supported by the C9xx cores (e.g., found in
the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBs is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Depends on D143394

Differential Revision: https://reviews.llvm.org/D143036
 2023-02-08 07:57:27 +01:00
Philipp Tomsich
e25b30d90a [RISCV] Add vendor-defined XTHeadBa (address-generation) extension 
The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143029
 2023-02-08 07:54:52 +01:00
Craig Topper
c7449c1770 [RISCV] Refactor RISCVDisassembler::getInstruction to remove repeated code. NFC 
For 4 byte instructions we were always setting size to 4 eventually. Same
for 2 byte instructions. So do it as soon as we know the from the opcode.

Add a return to the end of the 4 byte code so we don't have to have an else
around the 2 byte code.

Differential Revision: https://reviews.llvm.org/D143445
 2023-02-06 21:23:21 -08:00
Craig Topper
2398e2057c [RISCV] Remove DecoderMethod from C_NOP_HINT. NFC 
This doesn't appear to be needed.

Differential Revision: https://reviews.llvm.org/D143367
 2023-02-06 07:25:56 -08:00
Philipp Tomsich
ba8b8a73fc [RISCV][NFC] Update debug message for XTHeadVdot 
As we prepare the tree to add more vendor-defined extensions that are
originating with T-Head, the debug message announcing the XTheadVdot
decoder namespace should refer to XTHeadVdot instead of all T-Head
custom extensions.
 2023-02-06 10:12:34 +01:00
Craig Topper
3a606785c5 [RISCV] Use uint32_t intead of uint64_t for instruction fields in RISCVDisassembler.cpp. NFC 
The tablegen generated code is templated based on the type of Insn
passed to decodeInstruction which is currently uint32_t. All of the
fields extracted will this type.
 2023-02-05 23:44:12 -08:00
Craig Topper
d2fd0d3cbc [RISCV] Simplify some code in RISCVDisassembler. NFC 
Create X0 register directly instead of passing 0 to DecodeGPRRegisterClass.
 2023-02-05 23:44:12 -08:00
Craig Topper
b3ab26b4aa [RISCV] Fix bug where C_ADDI_HINT_IMM_ZERO was incorrectly disassembled as C_ADDI. 
And was then printed as 'mv'.
 2023-02-05 12:31:36 -08:00