22478 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
a168ddc470
[MLIR][LLVM] Block address support (#134335)
Add support for import and translate.

MLIR does not support using basic block references outside a function
(like LLVM does), This PR does not consider changes to MLIR to that
respect. It instead introduces two new ops: `llvm.blockaddress` and
`llvm.blocktag`. Here's an example:

```
llvm.func @ba() -> !llvm.ptr {
  %0 = llvm.blockaddress <function = @ba, tag = <id = 1>> : !llvm.ptr
  llvm.br ^bb1
^bb1:  // pred: ^bb0
  llvm.blocktag <id = 1>
  llvm.return %0 : !llvm.ptr
}
```

Value `%0` hold the address of block tagged as `id = 1` in function
`@ba`. Block tags need to be unique within a function and use of
`llvm.blockaddress` requires a matching tag in a `llvm.blocktag`.
2025-04-07 17:53:18 -07:00
Jerry-Ge
a38ad6e2a2
[mlir][tosa] Check empty Concat input for inferReturnTypeComponents (#134728)
Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-07 16:27:08 -07:00
Jan Leyonberg
fbc8335311
[MLIR][OpenMP] Add codegen for teams reductions (#133310)
This patch adds the lowering of teams reductions from the omp dialect to
LLVM-IR. Some minor cleanup was done in clang to remove an unused
parameter.
2025-04-07 12:47:16 -04:00
Tai Ly
cb9afe53bf
[mlir][tosa] Fix validation pass assert (#134445)
This fixes a validation pass assert when processing ops with quantized
element types.
The failure case is added to invalid.mlir
The fix is to re-order the validation checking so that only ops with
int/float operands and results pass the first stage of validation pass,
so that the remaining checks do not need to handle quantized data types.

Signed-off-by: Tai Ly <tai.ly@arm.com>
2025-04-07 09:47:07 -07:00
Jerry-Ge
112af87964
[mlir][tosa] Add parenthesis for the weight padding calculation (#134420)
Minor change.

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-07 09:43:46 -07:00
Igor Wodiany
cff65657d9
[mlir][spirv] Fix incorrect argument erasure in deserializer (#134610)
The current implementation iterates and modifies the list of arguments
at the same time. Depending on the number of arguments this will trigger
an assert: `assert(index < arguments.size())`. This change replaces loop
with a range based erasure.
2025-04-07 15:00:33 +01:00
Andrzej Warzyński
2f6bc47a18
[mlir][vector] Standardise valueToStore Naming Across Vector Ops (NFC) (#134206)
This change standardises the naming convention for the argument
representing the value to store in various vector operations.
Specifically, it ensures that all vector ops storing a value—whether
into memory, a tensor, or another vector — use `valueToStore` for the
corresponding argument name.

Updated operations:
* `vector.transfer_write`, `vector.insert`, `vector.scalable_insert`,
  `vector.insert_strided_slice`.

For reference, here are operations that currently use `valueToStore`:
* `vector.store` `vector.scatter`, `vector.compressstore`,
  `vector.maskedstore`.

This change is non-functional (NFC) and does not affect the
functionality of these operations.

Implements #131602
2025-04-07 13:56:54 +01:00
Matthias Springer
bafa2f4442
[mlir][memref] Check memory space before lowering alloc ops (#134427)
Check the memory space before lowering allocation ops, instead of
starting the lowering and then rolling back the pattern when the memory
space was found to be incompatible with LLVM.

Note: This is in preparation of the One-Shot Dialect Conversion
refactoring.

Note: `isConvertibleAndHasIdentityMaps` now also checks the memory
space.
2025-04-07 14:38:18 +02:00
Uday Bondhugula
37deb09593
[MLIR][Affine] Fix signatures of normalize memref utilities (#134466)
These methods were passing derived op types by pointers, which deviates
from the style. While on this, fix obsolete comments on those methods.
2025-04-07 17:36:28 +05:30
Jorn Tuyls
96de8435b9
[mlir][NVVM] Fix default label unreachable warning in getVoteSyncIntrinsicId (#134600)
Fixes the following warning after the changes in
https://github.com/llvm/llvm-project/pull/134309:

```
llvm-project/mlir/lib/Target/LLVMIR/Dialect/NVVM/NVVMToLLVMIRTranslation.cpp:134:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
  default:
  ^
1 warning generated.
```
2025-04-07 13:13:02 +02:00
Jack Frankland
7b007c092d
[mlir][tosa-to-linalg] Add acc_type lowering Support (#134267)
Add support for lowering of convolution operations where the `acc_type`
attribute differs from the result type of the operation. The only case
of this in for convolutions in the TOSA-v1.0 specification is an fp16
convolution which internally uses an fp32 accumulator; all other
operations have accumulator types that match their output/result types.

Add lit tests for the fp16 convolution with fp32 accumulator operators
described above.

Signed-off-by: Jack Frankland <jack.frankland@arm.com>
2025-04-07 11:37:26 +01:00
Matthias Springer
431c8dd073
[mlir][IR] Add support for UnknownLoc to verify-diagnostics (#134421)
Diagnostics at unknown locations can now be verified with
`-verify-diagnostics`.

Example:
```
// expected-error@unknown {{something went wrong}}
```

Also clean up some MemRefToLLVM conversion tests that had to redirect
all errors to stdout in order to FileCheck them. All of those tests can
now be stored in a single `invalid.mlir`. That was not possible before.
2025-04-07 12:03:04 +02:00
Mike
f20cb3f8d2
[mlir][bufferization] Drop the assumption for alloc result index (#134503)
Relax the assumption that alloc op always has allocation at
`getResult(0)`, allow to use `optimize-allocation-liveness` pass for
custom ops with >1 results. Ops with multiple allocations are not
handled here yet.
2025-04-07 11:54:44 +03:00
Tobias Gysi
d9ccfd7568
[mlir][llvm] Respect call noinline attr in inliner (#134493)
This commit extends the LLVM dialect inliner interface to respect the
call op's noinline attribute. This is a follow-up to
https://github.com/llvm/llvm-project/pull/133726
which added the noinline attribute to the LLVM dialect call op.
2025-04-07 08:12:46 +02:00
Benjamin Kramer
3e08dcd767 [mlir][inliner] Move callback types from InlinerConfig -> InlinerInterface. NFC.
The proper layering here is that Inliner depends on InlinerUtils, and
not the other way round. Maybe it's time to give InliningUtils a less
terrible file name.
2025-04-06 13:02:42 +02:00
junfengd-nv
aeec94500a
[mlir][inliner] Add doClone and canHandleMultipleBlocks callbacks to Inliner Config (#131226)
Current inliner disables inlining when the caller is in a region with
single block trait, while the callee function contains multiple blocks.
the SingleBlock trait is used in operations such as do/while loop, for
example fir.do_loop, fir.iterate_while and fir.if. Typically, calls within
loops are good candidates for inlining. However, functions with multiple
blocks are also common. for example, any function with "if () then
return" will result in multiple blocks in MLIR.

This change gives the flexibility of a customized inliner to handle such
cases.
doClone: clones instructions and other information from the callee
function into the caller function. .
canHandleMultipleBlocks: checks if functions with multiple blocks can be
inlined into a region with the SingleBlock trait.

The default behavior of the inliner remains unchanged.

---------

Co-authored-by: jeanPerier <jean.perier.polytechnique@gmail.com>
Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
2025-04-05 22:56:55 +02:00
Matthias Springer
68ce637872
[mlir][Transforms][NFC] Dialect Conversion: Replace after legalizing constants (#134384)
When folding an op during a conversion, first try to legalize all
generated constants, then replace the original operation. This is
slightly more efficient because fewer rewrites must be rolled back in
case a generated constant could not be legalized.

Note: This is in preparation of the One-Shot Dialect Conversion
refactoring.
2025-04-05 06:20:25 -07:00
Florian Hahn
13799998c0
[EquivalenceClasses] Use DenseMap instead of std::set. (NFC) (#134264)
Replace the std::set with DenseMap, which removes the requirement for an
ordering predicate. This also requires to allocate the ECValue objects
separately. This patch uses a BumpPtrAllocator.

Follow-up to https://github.com/llvm/llvm-project/pull/134075.

Compile-time impact is mostly neutral or slightly positive:

https://llvm-compile-time-tracker.com/compare.php?from=ee4e8197fa67dd1ed6e9470e00708e7feeaacd97&to=242e6a8e42889eebfc0bb5d433a4de7dd9e224a7&stat=instructions:u
2025-04-05 12:24:39 +01:00
Jerry-Ge
64b060f129
[mlir][tosa] Update URLs to TOSA specification (#134449)
- The existing URLs are no longer valid, updated to the current one

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-04 15:41:05 -07:00
Valentin Clement (バレンタイン クレメン)
cd2f85a24b
[mlir][NVVM] Add ops for vote all and any sync (#134309)
Add operations for `nvvm.vote.all.sync` and `nvvm.vote.any.sync`
intrinsics similar to `nvvm.vote.ballot.sync`.
2025-04-04 11:06:10 -07:00
Matthias Springer
5acab1bd15
[mlir][SPIRV] IfOpConversion: Compute result types earlier (#134380)
Compute the result types and bail out before modifying any IR. That is
more efficient when type conversion failed, because no modifications
must be rolled back.

Note: This is in preparation of the One-Shot Dialect Conversion
refactoring.
2025-04-04 09:37:15 -07:00
Kevin Gleason
e8d5009784
[mlir] Fix parsing of empty complex tensors (#134322)
After https://github.com/llvm/llvm-project/pull/133220 we had some empty
complex literals (`tensor<0xcomplex<f32>>`) failing to parse.

This was largely due to the ambiguity between `shape.empty()` meaning
splat (`dense<1>`) or empty literal (`dense<>`). Used type's numel to
disambiguate during verification.
2025-04-04 09:29:51 -07:00
Matthias Springer
6966b4f4a5
[mlir][arith] Remove func patterns from populateArithWideIntEmulationPatterns (#134316)
This function should populate only patterns that are related to wide
integer operation emulation.
2025-04-04 06:23:17 -07:00
Jerry-Ge
d6c076eeaa
[mlir][tosa] Reorder Tosa_ExtensionAttrs to match with definition order (#134319)
Simple refactor change.

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-04 11:33:52 +01:00
Alaa Ali
5812516ae2
[MLIR] Fix canonicalization pattern for 'shape.shape_of' (#134234)
This PR will fix a bug in a canonicalization pattern (operation
shape.shape_of: shape of reshape)

```
// Before
func.func @f(%arg0: tensor<?x1xf32>, %arg1: tensor<3xi32>) -> tensor<3xindex> {
  %reshape = tensor.reshape %arg0(%arg1) : (tensor<?x1xf32>, tensor<3xi32>) -> tensor<?x1x1xf32>
  %0 = shape.shape_of %reshape : tensor<?x1x1xf32> -> tensor<3xindex>
  return %0 : tensor<3xindex>
}
//This is will error out as follows:
error: 'tensor.cast' op operand type 'tensor<3xi32>' and result type 'tensor<3xindex>' are cast incompatible
  %0 = shape.shape_of %reshape : tensor<?x1x1xf32> -> tensor<3xindex>
       ^
note: see current operation: %0 = "tensor.cast"(%arg1) : (tensor<3xi32>) -> tensor<3xindex>
```

```
// After
func.func @f(%arg0: tensor<?x1xf32>, %arg1: tensor<3xi32>) -> tensor<3xindex> {
  %0 = arith.index_cast %arg1 : tensor<3xi32> to tensor<3xindex>
  return %0 : tensor<3xindex>
}
```
See file canonicalize.mlir in the change list for an example.

For the context, this bug was found while running a test on Keras 3, the
canonicalizer errors out due to an invalid tensor.cast operation when
the batch size is dynamic.
The operands of the op are tensor<3xi32> cast to tensor<3xindex>.
This change is related to a previous PR:
https://github.com/llvm/llvm-project/pull/98531

---------

Co-authored-by: Alaa Ali <alaaali@ah-alaaali-l.dhcp.mathworks.com>
Co-authored-by: Mehdi Amini <joker.eph@gmail.com>
2025-04-04 11:46:58 +02:00
Adrian Kuegel
c154d66339 [mlir] Apply ClangTidyBugProne finding (NFC).
argument name 'outputType' in comment does not match parameter name 'outputTypes'
2025-04-04 09:01:56 +00:00
Igor Wodiany
9eb7e64145
[mlir][spirv] Add verification for Bias operand (#134231) 2025-04-04 09:41:54 +01:00
Iris
92923e517c
[mlir][llvm] Add LLVM_DependentLibrariesAttr (#133385)
https://llvm.org/docs/LangRef.html#dependent-libs-named-metadata

---------

Co-authored-by: Tobias Gysi <tobias.gysi@nextsilicon.com>
2025-04-04 08:00:04 +02:00
Jerry-Ge
7d05c2326c
[mlir][tosa] Remove extra trailing whitespace (#134290)
Trivial change.

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-03 18:15:39 -07:00
Jerry-Ge
fcfbef5582
[mlir][tosa] Remove extra declarations of MulOperandsAndResultElementType in TosaOps.td (#134300)
Minor code cleanup

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-03 18:15:30 -07:00
modiking
9f2feeb189
[mlir][gpu][nvptx] Remove null terminator when outputting PTX (#133019)
PTX source files are expected to only contain ASCII text
(https://docs.nvidia.com/cuda/parallel-thread-execution/#source-format) and no null terminators.

`ptxas` has so far not enforced this but is moving towards doing so.
This revealed a problem where the null terminator is getting printed out
in the output file in MLIR path when outputting ptx directly. Only add the null on the assembly output path for JIT instead of in output of `moduleToObject `.
2025-04-03 15:50:54 -07:00
MaheshRavishankar
a1bc979aa8
[mlir][Bufferization] Do not have read semantics for destination of tensor.parallel_insert_slice. (#134169)
`tensor.insert_slice` needs to have read semantics on its destination
operand. Since it has a return value, its semantics are

- Copy dest to result
- Copy source to subview of destination.

`tensor.parallel_insert_slice` though has no result. So it does not need
to have read semantics. The op description
[here](a3ac318e5f/mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td (L1524))
also says that it is expected to lower to a `memref.subview`, that does
not have read semantics on the destination (its just a view).

This patch drops the read semantics for destination of
`tensor.parallel_insert_slice` but also makes the `shared_outs` operands
of `scf.forall` have read semantics. Earlier it would rely indirectly on
read semantics of destination operand of `tensor.parallel_insert_slice`
to propagate the read semantics for `shared_outs`. Now that is specified
more directly.

Fixes #133964

---------

Signed-off-by: MaheshRavishankar <mahesh.ravishankar@gmail.com>
2025-04-03 09:47:36 -07:00
Sergio Afonso
f59b5b8d59
[MLIR][OpenMP] Fix standalone distribute on the device (#133094)
This patch updates the handling of target regions to set trip counts and
kernel execution modes properly, based on clang's behavior. This fixes a
race condition on `target teams distribute` constructs with no `parallel
do` loop inside.

This is how kernels are classified, after changes introduced in this
patch:

```f90
! Exec mode: SPMD.
! Trip count: Set.
!$omp target teams distribute parallel do
do i=...
end do

! Exec mode: Generic-SPMD.
! Trip count: Set (outer loop).
!$omp target teams distribute
do i=...
  !$omp parallel do private(idx, y)
  do j=...
  end do
end do

! Exec mode: Generic-SPMD.
! Trip count: Set (outer loop).
!$omp target teams distribute
do i=...
  !$omp parallel
    ...
  !$omp end parallel
end do

! Exec mode: Generic.
! Trip count: Set.
!$omp target teams distribute
do i=...
end do

! Exec mode: SPMD.
! Trip count: Not set.
!$omp target parallel do
do i=...
end do

! Exec mode: Generic.
! Trip count: Not set.
!$omp target
  ...
!$omp end target
```

For the split `target teams distribute + parallel do` case, clang
produces a Generic kernel which gets promoted to Generic-SPMD by the
openmp-opt pass. We can't currently replicate that behavior in flang
because our codegen for these constructs results in the introduction of
calls to the `kmpc_distribute_static_loop` family of functions, instead
of `kmpc_distribute_static_init`, which currently prevent promotion of
the kernel to Generic-SPMD.

For the time being, instead of relying on the openmp-opt pass, we look
at the MLIR representation to find the Generic-SPMD pattern and directly
tag the kernel as such during codegen. This is what we were already
doing, but incorrectly matching other kinds of kernels as such in the
process.
2025-04-03 15:41:00 +01:00
Sergio Afonso
18dd299fb1
[Flang][MLIR][OpenMP] Host-evaluation of omp.loop bounds (#133908)
This patch updates Flang lowering and kernel flags identification in
MLIR so that loop bounds on `target teams loop` constructs are evaluated
on the host, making the trip count available to the corresponding
`__tgt_target_kernel` call emitted for the target region.

This is necessary in order to properly execute these constructs as
`target teams distribute parallel do`.

Co-authored-by: Kareem Ergawy <kareem.ergawy@amd.com>
2025-04-03 15:06:19 +01:00
Frank Schlimbach
586c5e3083
[mlir][mpi] fixing in-place and 0d mpi.all_reduce (#134225)
* inplace allreduce needs special MPI token MPI_IN_PLACE as send buffer
* 0d tensors have no sizes/strides in LLVM memref struct
2025-04-03 15:53:40 +02:00
Elen Kalda
c2355892a4
[mlir][tosa] Add ERROR_IF checks to TRANSPOSE_CONV2D verifier (#133234)
This patch extends the verifier with following checks:

ERROR_IF(out_pad_top <= -KH || out_pad_bottom <= -KH);
ERROR_IF(out_pad_left <= -KW || out_pad_right <= -KW); ERROR_IF(stride_y
< 1 || stride_x < 1);
ERROR_IF(OH != (IH - 1) * stride_y + out_pad_top + out_pad_bottom + KH);
ERROR_IF(OW != (IW - 1) * stride_x + out_pad_left + out_pad_right + KW);
ERROR_IF(BC != OC && BC != 1);

Signed-off-by: Elen Kalda <elen.kalda@arm.com>
2025-04-03 14:04:28 +01:00
Hsiangkai Wang
2e7ed78cff
[mlir][spirv] Add instruction OpGroupNonUniformRotateKHR (#133428)
Add an instruction under the extension SPV_KHR_subgroup_rotate.

The specification for the extension is here:

https://github.khronos.org/SPIRV-Registry/extensions/KHR/SPV_KHR_subgroup_rotate.html
2025-04-03 11:00:29 +01:00
Jack Frankland
6f324bd39b
[mlir][tosa] Remove Convolution Type Verifiers (#134077)
Remove the test in the convolution verifier that checks the input and
output element types of convolution operations conform to the
constraints imposed by the TOSA 1.0 specification.

These checks are too strict for users of the TOSA dialect who wish to
allow more types than those allowed by the spec and provide
compatibility issues with earlier TOSA implementation which allowed more
type combinations.

Users who do wish to constrain the convolution types combination to only
those allowed by the TOSA 1.0 spec should run the TOSA validation pass
which already performs these checks.

Signed-off-by: Jack Frankland <jack.frankland@arm.com>
2025-04-03 10:30:10 +01:00
Jerry-Ge
94dbe5e405
[mlir][tosa] Remove extra whitespace in the PadOp example (#134113)
Trivial cleanup change.

Signed-off-by: Jerry Ge <jerry.ge@arm.com>
2025-04-02 19:40:54 -07:00
Nirvedh Meshram
42b3f91fd6
[mlir] Vectorize tensor.pad with low padding for unit dims (#133808)
We currently do not have masked vectorization support for tenor.pad with
low padding. However, we can allow this in the special case where the
result dimension after padding is a unit dim. The reason is when we
actually have a low pad on a unit dim, the input size of that dimension
will be (or should be for correct IR) dynamically zero and hence we will
create a zero mask which is correct. If the low pad is dynamically zero
then the lowering is correct as well.

---------

Signed-off-by: Nirvedh <nirvedh@gmail.com>
2025-04-02 16:32:36 -05:00
Andrzej Warzyński
2bee24632f
[mlir][bugfix] Fix erroneous condition in getEffectsOnResource (#133638)
This patch corrects an invalid condition in `getEffectsOnResource` used
to identify relevant "resources":

```cpp
return it.getResource() != resource;
```

The current implementation assumes that only one instance of each
resource will exist, so comparing raw pointers is both safe and
sufficient. This assumption stems from constructs like:

```cpp
static DerivedResource *get() {
  static DerivedResource instance;
  return &instance;
}
```
i.e., resource instances returned via static singleton methods.

However, as discussed in
 * https://github.com/llvm/llvm-project/issues/129216,

this assumption breaks in practice — notably on macOS (Apple Silicon)
when built with:

* `-DBUILD_SHARED_LIBS=On`.

In such cases, multiple instances of the same logical resource may exist
across shared library boundaries, leading to incorrect behavior and
causing failures in tests like:

* test/Dialect/Transform/check-use-after-free.mlir

This patch replaces the pointer comparison with a comparison based on
resource identity:

```cpp
return it.getResource()->getResourceID() != resource->getResourceID();
```
This approach aligns better with the intent of `getEffectsOnResource`,
which is to:

```cpp
/// Collect all of the effect instances that operate on the provided
/// resource (...)
```

Fixes #129216
2025-04-02 21:26:41 +01:00
ofri frishman
6f1347d57b
[MLIR] Bubble up tensor.extract_slice through tensor.collapse_shape (#131982)
Add a pattern that bubbles up tensor.extract_slice through
tensor.collapse_shape.
The pattern is registered in a pattern population function that is used
by the transform op
transform.apply_patterns.tensor.bubble_up_extract_slice and by the
tranform op transform.structured.fuse as a cleanup pattern.
This pattern enables tiling and fusing op chains which contain
tensor.collapse_shape if added as a cleanup pattern of tile and fuse
utility.
Without this pattern that would not be possible, as
tensor.collapse_shape does not implement the tiling interface. This is
an additional pattern to the one added in PR #126898
2025-04-02 21:06:43 +01:00
AdityaK
340f06a8d4
Fix: bail out when divisor is zero (#133518)
Fixes: #131279
2025-04-02 09:44:18 -07:00
Fehr Mathieu
8b67f36258
[mlir] [arith] Fix ceildivsi lowering in arith-expand (#133774)
This fixes the current lowering of `arith.ceildivsi` in the arith-expand
pass, which was previously incorrect. The new version is based on the
lowering of `arith.floordivsi`, and will not introduce new undefined
behavior or poison during the lowering. It also replaces one division
with a multiplication.

The previous lowering of `ceildivsi(n, m)` was the following:
```
x = (m > 0) ? -1 : 1
(n*m>0) ? ((n+x) / m) + 1 : - (-n / m)
```

This caused two problems:
* In the case where `n` is INT_MIN and `m` is positive, the result would
be poison instead of an actual value
* In the case where `n` is INT_MAX and `m` is `-1`, this would trigger
undefined behavior, while the original code wouldn't. This is because
`n+x` would be equal to `INT_MIN` (`INT_MAX + 1`), so the `(n+x) / m`
division would overflow and trigger UB.
2025-04-02 17:26:58 +01:00
Shilei Tian
84cb08e118
[MLIR][AMDGPU] Bump to COV6 (#133849)
We already bump to COV6 by default in the front-end and backend. This PR
is for MLIR.

Note that COV6 requires ROCm 6.3+.
2025-04-02 12:14:24 -04:00
Igor Wodiany
200b589a1b
[mlir][spirv] Fix ambiguous conversion between SmallVector and TypeRange (#134087)
This address buildbot failures caused by #133702.
2025-04-02 15:09:36 +01:00
Igor Wodiany
2a90631841
[mlir][spirv] Allow yielding values from selection regions (#133702)
There are cases in SPIR-V shaders where values need to be yielded from
the selection region to make valid MLIR. For example (part of the SPIR-V
shader decompiled to GLSL):

```
bool _115
if (_107)
{
    // ...
    float _200 = fma(...);
    // ...
    _115 = _200 < _174;
}
else
{
    _115 = _107;
}
bool _123;
if (_115)
{
    // ...
    float _213 = fma(...);
    // ...
    _123 = _213 < _174;
}
else
{
    _123 = _115;
}
````

This patch extends `mlir.selection` so it can return values.
`mlir.merge` is used as a "yield" operation. This allows to maintain a
compatibility with code that does not yield any values, as well as, to
maintain an assumption that `mlir.merge` is the only operation in the
merge block of the selection region.
2025-04-02 14:35:22 +01:00
Longsheng Mou
7d441d9892
[mlir] Use dyn_cast instead of cast in MathToVCIX conversion (#134047)
Fixes #131093.
2025-04-02 18:30:42 +08:00
Kazu Hirata
f1025c0e87
[mlir] Construct SmallVector with ArrayRef (NFC) (#134023) 2025-04-01 22:00:01 -07:00
Kazu Hirata
d760dbe6eb
[mlir] Remove extraneous calls to make_range (NFC) (#134020) 2025-04-01 21:59:51 -07:00