815 Commits

Author SHA1 Message Date
David Blaikie
40f842de9c Remove use of uniform initialization ({}) introduced in r212725 since this isn't supported in MSVC.
llvm-svn: 212754
2014-07-10 18:46:15 +00:00
Zinovy Nis
1db9573f03 [x32] Adding X32 target support to driver, including TargetInfo,DescriptionString, flags, paths lookup, etc. Cover changes with new tests. The author of the patch is Pavel Chupin (@pavel.v.chupin).
The changes enable "hello world" on x32 target (x86_64-*-linux-gnux32). s/isX32/IsX32/ also fixed.

Differential Revision: http://reviews.llvm.org/D4180

llvm-svn: 212725
2014-07-10 15:27:19 +00:00
Daniel Sanders
9500d2d751 [mips][mips64r6] Define _MIPS_FPSET, __mips_fpr, and __mips_nan2008 correctly on MIPS32r6/MIPS64r6
Summary:
This removes the need to pass -mnan=2008 explicitly to be able to compile
the test-suite for MIPS32r6/MIPS64r6.

Differential Revision: http://reviews.llvm.org/D4433

llvm-svn: 212619
2014-07-09 13:56:23 +00:00
Daniel Sanders
cfbb71dfb6 [mips] clz is defined to give 32 for zero. Similarly, dclz gives 64.
Summary:
While debugging another issue, I noticed that Mips currently specifies that the
count leading zero builtins are undefined when the input is zero. The
architecture specifications say that the clz and dclz instructions write 32 or
64 respectively when given zero.

This doesn't fix any bugs that I'm aware of but it may improve optimisation in
some cases.

Differential Revision: http://reviews.llvm.org/D4431

llvm-svn: 212618
2014-07-09 13:43:19 +00:00
Tim Northover
e8c3721165 ARM: use LLVM's atomicrmw instructions when ldrex/strex are available.
Having some kind of weird kernel-assisted ABI for these when the
native instructions are available appears to be (and should be) the
exception; OSs have been gradually opting in for years and the code
was getting silly.

So let LLVM decide whether it's possible/profitable to inline them by
default.

Patch by Phoebe Buckheister.

llvm-svn: 212598
2014-07-09 09:24:43 +00:00
Alp Toker
80758084f7 Use non-intrusive refcounting for TargetOptions
llvm-svn: 212388
2014-07-06 05:26:44 +00:00
Simon Atanasyan
4e16a4250d [Driver][Mips] Support one more MIPS CPU name - octeon.
llvm-svn: 212339
2014-07-04 12:37:04 +00:00
Simon Atanasyan
26610c5960 [Driver][Mips] Support more MIPS CPU names: mips1 - mips5.
llvm-svn: 212338
2014-07-04 12:36:56 +00:00
Simon Atanasyan
6b3544eb1d [Driver][Mips] Check MIPS CPU name provided to the Clang driver.
llvm-svn: 212260
2014-07-03 08:31:23 +00:00
Saleem Abdulrasool
4bddd9d400 CodeGen: make target builtins support languages
This extends the target builtin support to allow language specific annotations
(i.e. LANGBUILTIN).  This is to allow MSVC compatibility whilst retaining the
ability to have EABI targets use a __builtin_ prefix.  This is merely to allow
uniformity in the EABI case where the unprefixed name is provided as an alias in
the header.

llvm-svn: 212196
2014-07-02 17:41:27 +00:00
Tim Northover
1471cb17ae X86: inline all atomic operations up to 128-bits.
The backend *can* cope with all of these now, so Clang should give it the
chance. On CPUs without cmpxchg16b (e.g. the original athlon64) LLVM can reform
the libcalls.

rdar://problem/13496295

llvm-svn: 212173
2014-07-02 10:25:45 +00:00
David Majnemer
f607234fde Driver: Handle /GR- in a compatible way with MSVC
There are slight differences between /GR- and -fno-rtti which made
mapping one to the other inappropriate.

-fno-rtti disables dynamic_cast, typeid, and does not emit RTTI related
information for the v-table.

/GR- does not generate complete object locators and thus will not
reference them in vftables.  However, constructs like dynamic_cast and
typeid are permitted.

This should bring our implementation of RTTI up to semantic parity with
MSVC modulo bugs.

llvm-svn: 212138
2014-07-01 22:24:56 +00:00
Simon Atanasyan
ad80595b60 [Driver][Mips] MIPS ABI names "32" and "64" used as arguments of the "-mabi"
command line option only. Internally we convert them to the "o32" and "n64"
respectively. So we do not need to refer them anywhere after that conversion.

No functional changes.

llvm-svn: 212096
2014-07-01 10:59:09 +00:00
Saleem Abdulrasool
521cec84ac Basic: correct the va_list type on Windows on ARM
Windows on ARM defines va_list as a typedef for char *.  Although the semantics
of argument passing for variadic functions matches AAPCS VFP, the wrapped
struct __va_list type is unused.  This makes the intrinsic definition for
va_list match that of Visual Studio.

llvm-svn: 212004
2014-06-29 23:05:41 +00:00
Saleem Abdulrasool
24bd7da2d2 Basic: fix handling for Windows Itanium environment
This corrects the handling for i686-windows-itanium.  This environment is nearly
identical to Windows MSVC, except it uses the itanium ABI for C++.

llvm-svn: 211991
2014-06-28 23:34:11 +00:00
Saleem Abdulrasool
d1ee08e7cd Basic: whitespace cleanup
Remove unnecessary separation of anonymous namespace.  NFC.

llvm-svn: 211990
2014-06-28 23:34:07 +00:00
Simon Atanasyan
98ba8a657d [Driver][Mips] Fix else-after-return.
No functional changes.

llvm-svn: 211984
2014-06-28 15:56:08 +00:00
Simon Atanasyan
755d7f9c28 [Driver][Mips] Remove redundant brackets.
No functional changes.

llvm-svn: 211983
2014-06-28 15:56:03 +00:00
Simon Atanasyan
9601e6bfaa [Driver][Mips] Remove redundant abstract/override function.
No functional changes.

llvm-svn: 211982
2014-06-28 15:55:55 +00:00
Yi Kong
a44c4d7173 Introduce arm_acle.h supporting existing LLVM builtin intrinsics
Summary: This patch introduces ACLE header file, implementing extensions that can be directly mapped to existing Clang intrinsics. It implements for both AArch32 and AArch64.

Reviewers: t.p.northover, compnerd, rengolin

Reviewed By: compnerd, rengolin

Subscribers: rnk, echristo, compnerd, aemerson, mroth, cfe-commits

Differential Revision: http://reviews.llvm.org/D4296

llvm-svn: 211962
2014-06-27 21:25:42 +00:00
Jim Grosbach
be83cb8c96 ARM: Correctly identify cortex-m4 as v7em.
Get the predefined macro for the architecture correct.
cortex-m4: __ARM_ARCH_7EM__
cortex-m3: __ARM_ARCH_7M__
cortex-m0: __ARM_ARCH_6M__

rdar://17420090

llvm-svn: 211792
2014-06-26 17:24:16 +00:00
Will Schmidt
f048751912 Add ppc64/power8 as a target
llvm-svn: 211778
2014-06-26 13:34:10 +00:00
Matt Arsenault
56f008d538 Add R600 builtin codegen.
llvm-svn: 211631
2014-06-24 20:45:01 +00:00
Saleem Abdulrasool
9d45e77dca Driver: enhance MSC version compatibility
The version information for Visual Studio is spread over multiple variables.
The newer Windows SDK has started making use of some of the extended versioning
variables that were previously undefined.  Enhance our compatibility definitions
for these cases.

_MSC_VER is defined to be the Major * 100 + Minor.  _MSC_FULL_VER is defined to
be Major * 10000000 + Minor * 100000 + Build.  And _MSC_BUILD is the build
revision of the compiler.

Extend the -fmsc-version option in a compatible manner.  If the value is the
previous form of MMmm, then we assume that the build number is 0.  Otherwise, a
specific build number may be passed by using the form MMmmbbbbb.  Due to
bitwidth limitations of the option, it is currently not possible to define a
revision value.

The version information can be passed as either the decimal encoded value
(_MSC_FULL_VER or _MSC_VER) or as a dot-delimited value.

The change to the TextDiagnostic is to deal with the updated encoding of the
version information.

llvm-svn: 211420
2014-06-20 22:58:35 +00:00
Saleem Abdulrasool
0e3258cea8 Preprocessor: improve ACLE 6.4.1, 6.4.2 support
This improves conformance with ACLE 6.4.1.  Define additional macros that
indicate support for the ARM and Thumb instruction set architecture.  This
includes the following set of macros:

  __ARM_ARCH
  __ARM_ARCH_ISA_ARM
  __ARM_ARCH_ISA_THUMB
  __ARM_32BIT_STATE

These help identify the environment that the code is intended to execute on.

Adjust the handling for ACLE 6.4.2 to be more correct.  We would define the
profile as a free-standing token rather than a quoted single character.

llvm-svn: 210991
2014-06-15 18:35:07 +00:00
Kevin Qin
afd8847189 [AArch64] Add default features for CPUs on AArch64 target.
For ARM target, we can use CRYPTO and CRC features if we select
cortex-a57 by '-mcpu', but for AArch64 target, it doesn't work
unless adding with '-mfpu=crypto-neon-fp-armv8'. To keep consistency
between front-end and back-end and get end-users more easier to use,
we'd better add default feature for CPUs on AArch64 target as well.

llvm-svn: 210625
2014-06-11 01:42:16 +00:00
Alp Toker
4925ba7ffe StringRefize TargetInfo::getABI()
llvm-svn: 210402
2014-06-07 23:30:42 +00:00
Matheus Almeida
b84b37d606 [mips] Add macros _MIPS_ISA and __mips_isa_rev (same expansion as defined by GCC).
Summary: The Linux Kernel is one example of a piece of software that relies on them.

Reviewers: atanasyan

Reviewed By: atanasyan

Differential Revision: http://reviews.llvm.org/D3756

llvm-svn: 210270
2014-06-05 14:59:18 +00:00
Tim Northover
2a0783db23 AArch64: combine arm64 & aarch64 cases in switch
There shouldn't be any difference in behaviour here, at least not in
any configurations people care about and possibly not in any reachable
configurations.

llvm-svn: 209899
2014-05-30 14:14:07 +00:00
Tim Northover
573cbee543 AArch64/ARM64: rename ARM64 components to AArch64
This keeps Clang consistent with backend naming conventions.

llvm-svn: 209579
2014-05-24 12:52:07 +00:00
Tim Northover
25e8a6754e AArch64/ARM64: update Clang after AArch64 removal.
A few (mostly CodeGen) parts of Clang were tightly coupled to the
AArch64 backend. Now that it's gone, they will not even compile.

I've also deduplicated RUN lines in many of the AArch64 tests. This
might improve "make check-all" time noticably: some of those NEON
tests were monsters.

llvm-svn: 209578
2014-05-24 12:51:25 +00:00
Matt Arsenault
23e7b084b4 Update R600 datalayout
llvm-svn: 209464
2014-05-22 18:33:55 +00:00
Joerg Sonnenberger
cc1edb5a45 Add __ARM_DWARF_EH__ to signify the use of Itanium ABI for unwind
instructions.

llvm-svn: 208719
2014-05-13 18:58:36 +00:00
Craig Topper
f1186c5a8f [C++11] Use 'nullptr'.
llvm-svn: 208280
2014-05-08 06:41:40 +00:00
Matheus Almeida
602bff3184 [mips] Pass nan2008 info to the back-end.
Summary: The initial support for NaN2008 was added to the back-end in r206396.

Reviewers: atanasyan

Reviewed By: atanasyan

Differential Revision: http://reviews.llvm.org/D3448

llvm-svn: 208220
2014-05-07 16:16:07 +00:00
Saleem Abdulrasool
6323a2d63c Target: fix wchar_t definition for Windows on ARM
Windows on ARM uses AAPCS, but has some deviations.  wchar_t remains an unsigned
short on WoA, which does not conform to AAPCS.  Ensure that wchar_t is defined
accordingly.

llvm-svn: 207929
2014-05-04 01:56:04 +00:00
Benjamin Kramer
56c582279b Add support for -march=bdver4.
llvm-svn: 207848
2014-05-02 15:47:51 +00:00
Bradley Smith
9a6b29540e [ARM64/AArch64] Define the correct value for __ARM_NEON_FP
llvm-svn: 207842
2014-05-02 15:18:38 +00:00
Bradley Smith
418c5935f8 [ARM64/AArch64] Hook up CRC32 subtarget feature to the driver
llvm-svn: 207841
2014-05-02 15:17:51 +00:00
Richard Smith
7d3192fca5 Bitrig now supports TLS, so enable TLS support when targeting it. Patch by Patrick Wildt!
llvm-svn: 207812
2014-05-01 23:19:06 +00:00
Reid Kleckner
982a589d3a LLVM supports TLS on Windows and we can use it from Clang
Patch by Martell Malone!

Differential Revision: http://reviews.llvm.org/D3421

llvm-svn: 207470
2014-04-29 00:11:30 +00:00
Daniel Sanders
81ea601b54 [mips] Support 128-bit int in N32 ABI by overriding TargetInfo::hasInt128Type()
Summary: The condition in the base class is rather strange. It says a target has the 128-bit integer type if the size of a pointer is >= 64-bits. N32 has 32-bit pointers but 64-bit integers. I'm a bit reluctant to change this for all targets so this patch makes the method virtual and overrides it for MIPS64.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3472

llvm-svn: 207121
2014-04-24 16:05:26 +00:00
Daniel Sanders
ff1c044ada [mips] Correct size_t and ptrdiff_t for N32.
Summary:
Correct size_t to be unsigned int and ptrdiff_t to be signed long. The types were the correct size before this change but
the exact type matters for name mangling and exception handling in C++.

Reviewers: atanasyan

Reviewed By: atanasyan

Differential Revision: http://reviews.llvm.org/D3470

llvm-svn: 207093
2014-04-24 09:58:52 +00:00
James Molloy
8bdd24b1a9 [ARM64] Change inline assembly constraints to be more lax, to match the behaviour of Clang/AArch64 and GCC.
GCC allows sub-64bit values to use the 'r' register constraint.

llvm-svn: 206963
2014-04-23 10:26:19 +00:00
Reid Kleckner
70cfa66fe3 Try to fix bad Twine usage in r206791 with std::string
I'm pretty sure I was referencing destroyed temporaries here.  I'm open
to suggestions on how to write this better.

llvm-svn: 206804
2014-04-21 22:29:45 +00:00
Reid Kleckner
4760683b04 MinGW: Define __stdcall&co when -fms-extensions is disabled
This is for compatibility with GCC.

Reviewers: asl

Differential Revision: http://reviews.llvm.org/D3444

llvm-svn: 206791
2014-04-21 20:58:00 +00:00
James Molloy
ec78aa46f2 [ARM64] Teach Targets.cpp about Cortex-A53 and Cortex-A57, and enable more tests.
llvm-svn: 206463
2014-04-17 12:51:28 +00:00
Reid Kleckner
6f6e76dfe0 Revert "Move -fms-extensions predefined macros into InitPreprocessor"
This reverts commit r206413.

This was proposed before, but it's not clear if this is really a good
idea:
http://reviews.llvm.org/D3034

llvm-svn: 206415
2014-04-16 20:10:16 +00:00
Reid Kleckner
ae4759df00 Move -fms-extensions predefined macros into InitPreprocessor
If someone on Linux asks for -fms-extensions, there's no reason not to
define the feature test macros that MSVC defines.

llvm-svn: 206413
2014-04-16 19:47:06 +00:00
James Molloy
75f5f9e629 [ARM64] Allow the disabling of NEON and crypto instructions. Update tests to pass -target-feature +neon.
llvm-svn: 206394
2014-04-16 15:33:48 +00:00