mirrors/llvm-project
0
0
Fork 0
mirror of https://github.com/llvm/llvm-project.git synced 2025-05-04 18:06:06 +00:00
Code Issues Projects Releases Wiki Activity
97,326 Commits 1,258 Branches 288 Tags
Commit Graph

743 Commits

Author SHA1 Message Date
Jay Foad
583abbc4df PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() and 
zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method
trunc(), to be const and to return a new value instead of modifying the
object in place.

llvm-svn: 121120
 2010-12-07 08:25:19 +00:00
Bob Wilson
f9b96c474f Fix a comment typo. 
llvm-svn: 120235
 2010-11-28 06:51:19 +00:00
Wesley Peck
527da1b6e2 Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept. 
llvm-svn: 119990
 2010-11-23 03:31:01 +00:00
Duncan Sands
c92331b984 Fix thinko: we must turn select(anyext, sext) into sext(select) 
not anyext(select).  Spotted by Frits van Bommel.

llvm-svn: 119739
 2010-11-18 21:16:28 +00:00
Duncan Sands
12f3b3b44f The DAGCombiner was threading select over pairs of extending loads even 
if the extension types were not the same.  The result was that if you
fed a select with sext and zext loads, as in the testcase, then it
would get turned into a zext (or sext) of the select, which is wrong
in the cases when it should have been an sext (resp. zext).  Reported
and diagnosed by Sebastien Deldon.

llvm-svn: 119728
 2010-11-18 20:05:18 +00:00
Dan Gohman
5db8921422 Fix DAGCombiner to avoid folding a sext-in-reg or similar through a shl 
in order to fold it into a load.

llvm-svn: 118471
 2010-11-09 01:54:35 +00:00
Eric Christopher
c6418b105a Just return undef for invalid masks or elts, and since we're doing that, 
just do it earlier too.

llvm-svn: 118195
 2010-11-03 20:44:42 +00:00
Eric Christopher
fcc9e6848a If we have an undef mask our Elt will be -1 for our access, handle 
this by using an undef as a pointer.

Fixes rdar://8625016

llvm-svn: 118164
 2010-11-03 09:36:40 +00:00
Dan Gohman
68fb004616 Fix DAGCombiner to avoid going into an infinite loop when it 
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.

llvm-svn: 118143
 2010-11-03 01:47:46 +00:00
Bob Wilson
08882be86c Remove DAG combiner patch to fold vector splats. Instcombiner does it now. 
llvm-svn: 117720
 2010-10-29 22:03:02 +00:00
Bob Wilson
f63da12be9 Teach the DAG combiner to fold a splat of a splat. Radar 8597790. 
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
 2010-10-28 17:06:14 +00:00
Dan Gohman
a94cc6dfe8 Make CodeGen TBAA-aware. 
llvm-svn: 116890
 2010-10-20 00:31:05 +00:00
Evan Cheng
c8d6cfd730 This DAG combine BRCOND transformation can look pass truncate of the operand: 
//   %a = ...                                                                                                                                                                                  
    //   %b = and i32 %a, 2                                                                                                                                                                        
    //   %c = srl i32 %b, 1                                                                                                                                                                        
    //   brcond i32 %c ...                                                                                                                                                                         
    //                                                                                                                                                                                             
    // into                                                                                                                                                                                        
    //                                                                                                                                                                                             
    //   %a = ...                                                                                                                                                                                  
    //   %b = and i32 %a, 2                                                                                                                                                                        
    //   %c = setcc eq %b, 0                                                                                                                                                                       
    //   brcond %c ...

Make sure it restores local variable N1, which corresponds to the condition operand if it fails to match.

This apparently breaks TCE but since that backend isn't in the tree I don't have a test for it.

llvm-svn: 115571
 2010-10-04 22:41:01 +00:00
Chris Lattner
a205055857 fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350 
llvm-svn: 115294
 2010-10-01 05:36:09 +00:00
Owen Anderson
3231d13ddd A select between a constant and zero, when fed by a bit test, can be efficiently 
lowered using a series of shifts.
Fixes <rdar://problem/8285015>.

llvm-svn: 114599
 2010-09-22 22:58:22 +00:00
Owen Anderson
5e65dfbb97 Reimplement r114460 in target-independent DAGCombine rather than target-dependent, by using 
the predicate to discover the number of sign bits.  Enhance X86's target lowering to provide
a useful response to this query.

llvm-svn: 114473
 2010-09-21 20:42:50 +00:00
Chris Lattner
676c61db0e update a bunch of code to use the MachinePointerInfo version of getStore. 
llvm-svn: 114461
 2010-09-21 18:41:36 +00:00
Chris Lattner
6963c1f789 eliminate an old SelectionDAG::getTruncStore method, propagating 
MachinePointerInfo around more.

llvm-svn: 114452
 2010-09-21 17:42:31 +00:00
Chris Lattner
3d178ed4d4 propagate MachinePointerInfo through various uses of the old 
SelectionDAG::getExtLoad overload, and eliminate it.

llvm-svn: 114446
 2010-09-21 17:04:51 +00:00
Chris Lattner
f72c3c08a4 convert dagcombine off the old form of getLoad. This fixes several bugs 
with SVOffset computation.

llvm-svn: 114442
 2010-09-21 16:08:50 +00:00
Chris Lattner
e32675253f simplify DAGCombiner::SimplifySelectOps step #2/2. 
llvm-svn: 114437
 2010-09-21 15:58:55 +00:00
Chris Lattner
254c445e63 substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps. 
no functionality change (step #1)

llvm-svn: 114436
 2010-09-21 15:46:59 +00:00
Chris Lattner
a35499e2af a few more trivial updates. This fixes PerformInsertVectorEltInMemory to not 
pass a completely incorrect SrcValue, which would result in a miscompile with
combiner-aa.

llvm-svn: 114411
 2010-09-21 07:32:19 +00:00
Owen Anderson
272ff94916 When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore, 
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.

llvm-svn: 114348
 2010-09-20 20:39:59 +00:00
Owen Anderson
7b8d2ae912 Revert r114312 while I sort out some issues. 
llvm-svn: 114313
 2010-09-19 21:01:26 +00:00
Owen Anderson
ff82f8a35b Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know, 
r114268 fixed the last of the blockers to enabling it.  I will be monitoring
for failures.

llvm-svn: 114312
 2010-09-19 19:51:55 +00:00
Dan Gohman
3c9b5f394b Don't narrow the load and store in a load+twiddle+store sequence unless 
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.

llvm-svn: 112861
 2010-09-02 21:18:42 +00:00
Nate Begeman
317b969ac5 Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself 
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.

llvm-svn: 109519
 2010-07-27 18:02:18 +00:00
Owen Anderson
9c271e2835 Remove r108639 now that it is handled by InstCombine instead. 
llvm-svn: 108688
 2010-07-19 08:10:24 +00:00
Owen Anderson
f7f9c8a2f7 Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions. 
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.

This fixed <rdar://problem/8197504>.

llvm-svn: 108639
 2010-07-18 08:47:54 +00:00
Duncan Sands
41b4a6b36a Convert some tab stops into spaces. 
llvm-svn: 108130
 2010-07-12 08:16:59 +00:00
Bob Wilson
21eed476e8 Reenable DAG combining for vector shuffles. It looks like it was temporarily 
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941
 2010-07-09 00:38:12 +00:00
Benjamin Kramer
0ae3f08c0d Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms. 
llvm-svn: 107868
 2010-07-08 12:09:56 +00:00
Evan Cheng
1c349f18f8 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake. 
llvm-svn: 107820
 2010-07-07 22:15:37 +00:00
Devang Patel
a3ca21b228 Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson
269a89fd3a Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they 
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.

llvm-svn: 107097
 2010-06-28 23:40:25 +00:00
Duncan Sands
2dc70bea54 Remove variables which are assigned to but for which the value 
is not used.  Spotted by gcc-4.6.

llvm-svn: 106854
 2010-06-25 14:48:39 +00:00
Dan Gohman
600f62b3ba Reapply r106634, now that the bug it exposed is fixed. 
llvm-svn: 106746
 2010-06-24 14:30:44 +00:00
Daniel Dunbar
4df321b7ad Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. 
llvm-svn: 106634
 2010-06-23 17:09:26 +00:00
Jim Grosbach
b58c08b0ba Some targets don't require the fencing MEMBARRIER instructions surrounding 
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.

llvm-svn: 106630
 2010-06-23 16:07:42 +00:00
Dan Gohman
b92156d5e4 Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.

llvm-svn: 106263
 2010-06-18 01:05:21 +00:00
Dale Johannesen
60fe2cdc4f Fix another variant of PR 7191. Also add a testcase 
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624
 2010-05-25 18:47:23 +00:00
Dale Johannesen
ff384ad981 Fix PR 7191. I have been unable to create a .ll file that fails, sorry. 
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619
 2010-05-25 17:50:03 +00:00
Bob Wilson
61438fe064 Clean up extra whitespace. 
llvm-svn: 104410
 2010-05-21 23:53:55 +00:00
Bob Wilson
51d9ee3ff6 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
 2010-05-21 21:05:32 +00:00
Bob Wilson
42603958fb Optimize away insertelement of an undef value. This shows up in 
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185
 2010-05-19 23:42:58 +00:00
Evan Cheng
abd0ad54a4 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
 2010-05-19 01:08:17 +00:00
Evan Cheng
f19384d54a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Evan Cheng
48f0de96d6 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 
llvm-svn: 104004
 2010-05-18 00:03:40 +00:00
Evan Cheng
02947a4551 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869. 
llvm-svn: 103419
 2010-05-10 19:03:57 +00:00