10784 Commits

Author SHA1 Message Date
Jack Styles
6aac30fa43
Update FEAT_PAuth_LR behaviour for AArch64 (#90614)
Currently, LLVM enables `-mbranch-protection=standard` as `bti+pac-ret`.
To align LLVM with the behaviour in GNU, this has been updated to
`bti+pac-ret+pc` when FEAT_PAuth_LR is enabled as an optional feature
via the `-mcpu=` options. If this is not enabled, then this will revert
to the existing behaviour.
2024-05-10 08:09:02 +01:00
Jonas Devlieghere
1e97d114b5
[dsymutil] Add -q/--quiet flag to suppress warnings (#91658)
Add a -q/--quiet flag to suppress dsymutil output. For now the flag is
limited to dsymutil, though there might be other places in the DWARF
linker that could be conditionalized by this flag.

The motivation is having a way to silence the "no debug symbols in
executable" warning. This is useful when we want to generate a dSYM for
a binary not containing debug symbols, but still want a dSYM that can be
indexed by spotlight.

rdar://127843467
2024-05-09 15:55:36 -07:00
Fangrui Song
aacea0d0f6
[utils] Add script to generate elaborated IR and assembly tests (#89026)
Generally, IR and assembly test files benefit from being cleaned to
remove unnecessary details. However, for tests requiring elaborate
IR or assembly files where cleanup is less practical (e.g., large amount
of debug information output from Clang), the current practice is to
include the C/C++ source file and the generation instructions as
comments.

This is inconvenient when regeneration is needed. This patch adds
`llvm/utils/update_test_body.py` to allow easier regeneration.

`ld.lld --debug-names` tests (#86508) utilize this script for
Clang-generated assembly tests.

Note: `-o pipefail` is standard (since
https://www.austingroupbugs.net/view.php?id=789) but not supported by
dash.

Link:
https://discourse.llvm.org/t/utility-to-generate-elaborated-assembly-ir-tests/78408
2024-05-08 23:58:55 -07:00
Mircea Trofin
96568f3539
[llvm][ctx_profile] Add instrumentation lowering (#90821)
This adds the instrumentation lowering pass.

(Tracking Issue: #89287, RFC referenced there)
2024-05-08 16:49:08 -07:00
XChy
08011cf845
[Docs][NFC] Use opaque ptr in the example (#91502) 2024-05-09 01:15:49 +08:00
Farzon Lotfi
3e82442ff7
[SPIRV] Add tan intrinsic part 3 (#90278)
This change is an implementation of #87367's investigation on supporting
IEEE math operations as intrinsics.
Which was discussed in this RFC:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294

If you want an overarching view of how this will all connect see:
https://github.com/llvm/llvm-project/pull/90088
Changes:
- `llvm/docs/GlobalISel/GenericOpcode.rst` - Document the `G_FTAN`
opcode
-  `llvm/include/llvm/IR/Intrinsics.td` - Create the tan intrinsic
- `llvm/include/llvm/Support/TargetOpcodes.def` - Create a `G_FTAN`
Opcode handler
- `llvm/include/llvm/Target/GenericOpcodes.td` - Define the `G_FTAN`
Opcode
- `llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp` Map the tan intrinsic
to `G_FTAN` Opcode
- `llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp` - Map the
`G_FTAN` opcode to the GLSL 4.5 and openCL tan instructions.
- `llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp` - Define `G_FTAN` as a
legal spirv target opcode.
2024-05-08 00:57:39 -04:00
Farzon Lotfi
31b45a9d0d
[clang][hlsl] Add tan intrinsic part 1 (#90276)
This change is an implementation of #87367's investigation on supporting
IEEE math operations as intrinsics.
Which was discussed in this RFC:
https://discourse.llvm.org/t/rfc-all-the-math-intrinsics/78294

If you want an overarching view of how this will all connect see:
https://github.com/llvm/llvm-project/pull/90088

Changes:
- `clang/docs/LanguageExtensions.rst` - Document the new elementwise tan
builtin.
-  `clang/include/clang/Basic/Builtins.td` - Implement the tan builtin.
- `clang/lib/CodeGen/CGBuiltin.cpp` - invoke the tan intrinsic on uses
of the builtin
- `clang/lib/Headers/hlsl/hlsl_intrinsics.h` - Associate the tan builtin
with the equivalent hlsl apis
- `clang/lib/Sema/SemaChecking.cpp` - Add generic sema checks as well as
HLSL specifc sema checks to the tan builtin
-  `llvm/include/llvm/IR/Intrinsics.td` - Create the tan intrinsic
-  `llvm/docs/LangRef.rst` - Document the tan intrinsic
2024-05-07 22:54:15 -04:00
Benji Smith
584253c4e2
[C API] Add getters and build function for CallBr (#91154)
This adds LLVMBuildCallBr to create CallBr instructions, and getters for
the CallBr-specific data. The remainder of its data, e.g.
arguments/function, can be accessed using existing getters.
2024-05-08 10:59:53 +09:00
Chris Copeland
651bdb96b1
[ARM] Armv8-R does not require fp64 or neon. (#88287)
This was [addressed for AArch64
here](https://github.com/llvm/llvm-project/pull/79004), but the same
applies to ARM.

Move the enablement of neon+fp64 to `-mcpu=cortex-r52`, which optionally
supports these features.
2024-05-07 11:48:30 +01:00
Peter Waller
1de0535e84
[llvm-mca] Abort on parse error without -skip-unsupported-instructions (#90474)
[llvm-mca] Abort on parse error without -skip-unsupported-instructions

Prior to this patch, llvm-mca would continue executing after parse
errors. These errors can lead to some confusion since some analysis
results are printed on the standard output, and they're printed after
the errors, which could otherwise be easy to miss.

However it is still useful to be able to continue analysis after errors;
so extend the recently added -skip-unsupported-instructions to support
this.

Two tests which have parse errors for some of the 'RUN' branches are
updated to use -skip-unsupported-instructions so they can remain as-is.

Add a description of -skip-unsupported-instructions to the llvm-mca
command guide, and add it to the llvm-mca --help output:

```
  --skip-unsupported-instructions=<value> - Force analysis to continue in the presence of unsupported instructions
    =none                                 -   Exit with an error when an instruction is unsupported for any reason (default)
    =lack-sched                           -   Skip instructions on input which lack scheduling information
    =parse-failure                        -   Skip lines on the input which fail to parse for any reason
    =any                                  -   Skip instructions or lines on input which are unsupported for any reason
```

Tests within this patch are intended to cover each of the cases.

Reason        | Flag | Comment
--------------|------|-------
none          | none | Usual case, existing test suite
lack-sched    | none | Advises user to use -skip-unsupported-instructions=lack-sched, tested in llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
parse-failure | none | Advises user to use -skip-unsupported-instructions=parse-failure, tested in llvm/test/tools/llvm-mca/bad-input.s
any           | none | (N/A, covered above)
lack-sched    | any  | Continues, prints warnings, tested in llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
parse-failure | any  | Continues, prints errors, tested in llvm/test/tools/llvm-mca/bad-input.s
lack-sched    | parse-failure | Advises user to use -skip-unsupported-instructions=lack-sched, tested in llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s
parse-failure | lack-sched    | Advises user to use -skip-unsupported-instructions=parse-failure, tested in llvm/test/tools/llvm-mca/bad-input.s
none          | * | This would be any test case with skip-unsupported-instructions, coverage added in llvm/test/tools/llvm-mca/X86/BtVer2/simple-test.s
any           | * | (Logically covered by the other cases)
2024-05-07 09:13:44 +01:00
Nikita Popov
de8cf69abf
[LangRef] callbr result can be used in all successors (#91167)
Originally, the callbr result could only be used on the fallthrough
destination. This limitation has been lifted, and the result is now also
available on the indirect destinations. However, LangRef was not updated
to reflect this.
2024-05-07 09:46:16 +09:00
Chris B
afeedd9c3d
[DirectX][docs] Document DXContainer format (#90908)
This adds a document to describe the DXContainer format and the
structures of data inside the file.

Resolves #88775
2024-05-06 16:20:31 -05:00
Matt Arsenault
d654278bde
Reapply "AMDGPU: Implement llvm.set.rounding (#88587)" series (#91113)
Revert "Revert 4 last AMDGPU commits to unbreak Windows bots"

This reverts commit 0d493ed2c6e664849a979b357a606dcd8273b03f.

MSVC does not like constexpr on the definition after an extern
declaration of a global.
2024-05-06 09:09:19 +02:00
Mehdi Amini
0d493ed2c6 Revert 4 last AMDGPU commits to unbreak Windows bots
Revert "AMDGPU: Try to fix build error with old gcc"
This reverts commit c7ad12d0d7606b0b9fb531b0b273bdc5f1490ddb.

Revert "AMDGPU: Use umin in set.rounding expansion"
This reverts commit a56f0b51dd988ad2b533de759c98457c1ed42456.

Revert "AMDGPU: Optimize set_rounding if input is known to fit in 2 bits (#88588)"
This reverts commit b4e751e2ab0ff152ed18dea59ebf9691e963e1dd.

Revert "AMDGPU: Implement llvm.set.rounding (#88587)"
This reverts commit 9731b77e80261c627d79980f8c275700bdaf6591.
2024-05-04 19:57:33 +02:00
Andreas Jonson
1343e68862
[C API] Add function to create ConstantRange attributes to C API (#90505) 2024-05-04 16:01:59 +09:00
Nikita Popov
f16e234f11
[InstCombine] Do not request non-splat vector support in code reviews (NFC) (#90709)
The InstCombine contributor guide already says:

> Handle non-splat vector constants if doing so is free, but do
> not add handling for them if it adds any additional complexity
> to the code.

This change strengthens this guideline to explicitly discourage
asking (new) contributors to implement non-splat support during code
reviews. Doing so will almost certainly increase the number of
necessary review iterations, or result in outright contradictory review
feedback, as different people are willing to accept a different degree
of complexity for non-splat vector support.
2024-05-04 16:01:36 +09:00
Maksim Levental
b958ef1948
Update GettingInvolved.rst (#91008) 2024-05-03 19:02:28 -05:00
Fangrui Song
121bef76df [docs,utils] Convert text files from CRLF to LF
Skip *.bat, *.natvis, utils/lit/tests/Inputs/shtest-shell/diff-in.dos
2024-05-03 10:16:54 -07:00
Stephen Tozer
91446e2aa6 Repply#2 "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"
Reapplies the original commit:
  2f01fd99eb8c8ab3db9aba72c4f00e31e9e60a05

The previous application of this patch failed due to some missing
DbgVariableRecord support in clang, which has been added now by commit
8805465e.

This will probably break some downstream tools that don't already handle
debug records. If your downstream code breaks as a result of this
change, the simplest fix is to convert the module in question to the old
debug format before you process it, using
`Module::convertFromNewDbgValues()`. For more information about how to
handle debug records or about what has changed, see the migration
document:
    https://llvm.org/docs/RemoveDIsDebugInfo.html

This reverts commit 4fd319ae273ed6c252f2067909c1abd9f6d97efa.
2024-05-03 12:55:31 +01:00
Matt Arsenault
9731b77e80
AMDGPU: Implement llvm.set.rounding (#88587)
Use a shift of a magic constant and some offseting to convert from
flt_rounds values.

I don't know why the enum defines Dynamic = 7. The standard suggests -1
is the cannot determine value. If we could start the extended values at
4 we wouldn't need the extra compare sub and select.

https://reviews.llvm.org/D153257
2024-05-03 09:41:27 +02:00
Stephen Tozer
4fd319ae27 Revert#2 "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"
Reverted following probably-causing failures on some clang buildbots:
  https://lab.llvm.org/buildbot/#/builders/245/builds/24037

This reverts commit a12622543de15df45fb9ad64e8ab723289d55169.
2024-05-02 17:52:02 +01:00
Craig Topper
44645996b0
[RISCV] Add smstateen extension (#90818) 2024-05-02 09:12:44 -07:00
Stephen Tozer
a12622543d Reapply "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"
Fixes the broken tests in the original commit:
  2f01fd99eb8c8ab3db9aba72c4f00e31e9e60a05

This will probably break some downstream tools that don't already handle
debug records. If your downstream code breaks as a result of this
change, the simplest fix is to convert the module in question to the old
debug format before you process it, using
`Module::convertFromNewDbgValues()`. For more information about how to
handle debug records or about what has changed, see the migration
document:
  https://llvm.org/docs/RemoveDIsDebugInfo.html

This reverts commit 00821fed09969305b0003d3313c44d1e761a7131.
2024-05-02 16:32:12 +01:00
Stephen Tozer
00821fed09 Revert "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"
A unit test was broken by the above commit:
  https://lab.llvm.org/buildbot/#/builders/139/builds/64627

This reverts commit 2f01fd99eb8c8ab3db9aba72c4f00e31e9e60a05.
2024-05-01 16:56:34 +01:00
Stephen Tozer
2f01fd99eb
[RemoveDIs] Load into new debug info format by default in LLVM (#89799)
This patch enables parsing and creating modules directly into the new
debug info format. Prior to this patch, all modules were constructed
with the old debug info format by default, and would be converted into
the new format just before running LLVM passes. This is an important
milestone, in that this means that every tool will now be exposed to
debug records, rather than those that run LLVM passes. As far as I've
tested, all LLVM tools/projects now either handle debug records, or
convert them to the old intrinsic format.

There are a few unit tests that need updating for this patch; these are
either cases of tests that previously needed to set the debug info
format to function, or tests that depend on the old debug info format in
some way. There should be no visible change in the output of any LLVM
tool as a result of this patch, although the likelihood of this patch
breaking downstream code means an NFC tag might be a little misleading,
if not technically incorrect:

This will probably break some downstream tools that don't already handle
debug records. If your downstream code breaks as a result of this
change, the simplest fix is to convert the module in question to the old
debug format before you process it, using
`Module::convertFromNewDbgValues()`. For more information about how to
handle debug records or about what has changed, see the migration
document:
  https://llvm.org/docs/RemoveDIsDebugInfo.html
2024-05-01 16:50:12 +01:00
Eli Friedman
a754ce0489 [LangRef] Fix build warning. 2024-04-30 10:33:37 -07:00
Eli Friedman
600cae7d42
[LangRef] Try to clarify mustprogress wording. (#90510)
Ensure it's clear that:

- Infinite loops in non-mustprogress functions are well-defined, even if
they're called by mustprogress functions.
- Infinite recursion in mustprogress functions is not well-defined.

Looking at D86233, it's clear this was the intent, but the "transitive"
wording is ambiguous. Instead, just explicitly state that infinite loops
written in non-mustprogress functions count as progress.
2024-04-30 10:16:12 -07:00
Min-Yih Hsu
539f626ecd
[VP][RISCV] Add vp.cttz.elts intrinsic and its RISC-V codegen (#90502)
This intrinsic is the VP version of `experimental.cttz.elts`.
2024-04-30 09:27:10 -07:00
Jonathan Thackray
e50a857fb1
[AArch64] Add support for Cortex-R82AE and improve Cortex-R82 (#90440) 2024-04-30 14:15:01 +01:00
Kristof Beyls
853344d3ae
[docs] Document which online sync-ups are no longer happening (#89361)
Some of the online sync-ups on our Getting Involved page seem to no
longer be happening. Document them as no longer happening, so that
people don't get confused when dialing in to one of these.
2024-04-30 09:49:57 +02:00
Maciej Gabka
bfc0317153
Move several vector intrinsics out of experimental namespace (#88748)
This patch is moving out following intrinsics:
* vector.interleave2/deinterleave2
* vector.reverse
* vector.splice

from the experimental namespace.

All these intrinsics exist in LLVM for more than a year now, and are
widely used, so should not be considered as experimental.
2024-04-29 10:16:45 +01:00
Sameer Sahasrabuddhe
256d76f480
[Docs] Improve the description of convergence (#89038)
- Clarify convergence of threads v/s convergence of operations.
- Explicitly address operations that are not in any cycle.

This was inspired by a discussion on Discourse:
https://discourse.llvm.org/t/llvm-convergence-semantics/77642
2024-04-28 19:56:14 +05:30
Craig Topper
b27f86b40b
[RISCV] Add an instruction PrettyPrinter to llvm-objdump (#90093)
This prints the opcode bytes in the same order as GNU objdump without a
space between them.
2024-04-26 11:27:28 -07:00
Jonathan Thackray
a670cdadca
[AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143)
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Neoverse-N3:
   https://developer.arm.com/documentation/107997/latest/

Technical Reference Manual for Neoverse-V3:
   https://developer.arm.com/documentation/107734/latest/

Technical Reference Manual for Neoverse-V3AE:
   https://developer.arm.com/documentation/101595/latest/
2024-04-26 13:04:35 +01:00
Alex Bradbury
357530f113 Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)"
This reverts commit 733b271db793ce30c504a1b5c4ae7a8775b0a6a2.

Reverting in order to revert the companion patch adding the atomics ABI
ELF attributes due to the reported incompatibility with GNU ld.
https://github.com/llvm/llvm-project/pull/84597#issuecomment-2079128332
2024-04-26 12:16:53 +01:00
bd1976bris
88a733f8e6
[llvm-objcopy][docs] Use "Mark" rather than "Make" in the objcopy docs for consistency (#90080)
llvm-objcopy --help uses the term "Mark" rather than "Make".
  e.g. "Mark all symbols local"
Change llvm/docs to align.
2024-04-26 09:13:17 +01:00
Thorsten Schütt
65fb80beae
[GlobalIsel] Add Gallery to MIR Patterns (#89974)
examples for fold of zext(trunc:nuw)
2024-04-26 07:06:49 +02:00
Paul Kirth
733b271db7
[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)
With the tag merging in place, we can safely change the default for
+seq-cst-trailing-fence to the default, according to the recommendation
in

https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc

This tag changes the default for the feature flag, and moves to more
consistent naming with respect to existing features.
2024-04-25 16:33:10 -07:00
Mircea Trofin
ddb67e6847
[llvm][ctx_profile] Add the llvm.instrprof.callsite intrinsic (#89939)
Add the callsite intrinsic. 

Structurally, it is very similar to the counter intrinsics, hence the inheritance relationship. We can probably rename `InstrProfCntrInstBase` to `InstrProfIndexedBase` later - because the "counting" aspect is really left to derived types of `InstrProfCntrInstBase`, and it only concerns itself with the index aspect (which is what we care about for `callsite`, too)

(Tracking Issue: #89287, RFC referenced there)
2024-04-25 15:00:09 -07:00
Andy Kaylor
2575cd8a90
Add ics link for Floating Point WG (#82545)
This adds a link to an ics file for the LLVM Floating Point WG line in
the Getting Involved page.
2024-04-24 11:55:17 -07:00
Scott Linder
69a3976e42 [AMDGPU][NFC] Fix typo in HeterogeneousDWARF doc 2024-04-24 17:38:54 +00:00
Hans Wennborg
93eeca331e LangRef: fix broken link 2024-04-24 14:59:37 +02:00
Pierre van Houtryve
cf328ff96d
[IR] Memory Model Relaxation Annotations (#78569)
Implements the core/target-agnostic components of Memory Model
Relaxation Annotations.

RFC:
https://discourse.llvm.org/t/rfc-mmras-memory-model-relaxation-annotations/76361/5
2024-04-24 08:52:25 +02:00
Andy Kaylor
5ac744d72a
[Nomination] New Intel representative for the security group (#89435)
Sergey Malsov has left Intel. I would like to nominate Will Huhn to replace him as an Intel representative in the LLVM security group. Will is a security champion for the Intel compiler team. I believe he will be a valuable addition to the LLVM security group as a second representative from Intel. He has more security-specific expertise than me. I regularly consult with Will about topics the LLVM security group is considering, and it will be useful to have him more directly involved.
2024-04-23 14:16:10 -07:00
Diana Picus
3ea9ed471c
[GlobalISel] Expand IRTranslator docs. NFC (#89186)
Add some more details about how calls are lowered and what APIs are
available.
2024-04-23 09:20:35 +02:00
Nathan Sidwell
2f7775775c
[docs] Rewrite cmake LLVM_RAM_PER_*_JOB description (#88570)
Rewrite  `LLVM_PARALLEL_{}_JOBS` and `LLVM_RAM_PER_{}_JOB` documentation.
2024-04-22 18:31:36 -04:00
Fangrui Song
89c95effe8
[llvm-readobj] Remove --raw-relr
https://reviews.llvm.org/D47919 dumped RELR relocations as
`R_*_RELATIVE` and added --raw-relr (not in GNU) for testing purposes
(more readable than `llvm-readelf -x .relr.dyn`). The option is obsolete
after `llvm-readelf -r` output gets improved (#89162).

Since --raw-relr never seems to get more adoption. Let's remove it to
avoid some complexity.

Pull Request: https://github.com/llvm/llvm-project/pull/89426
2024-04-22 12:35:04 -07:00
Matt Arsenault
dc9664a8ad
CodeGen: Strengthen definition of F{MIN|MAX}NUM_IEEE nodes (#85195)
Previously these were declared as having the 2008 behavior, with
underspecified signed zero handling. Currently, AMDGPU, PPC and
LoongArch mark these as legal. The AMDGPU and PPC instructions respect
the signed zero behavior. The LoongArch documentation doesn't state, but
I'm assuming it also does.
2024-04-22 10:13:04 +02:00
Aiden Grossman
b6824c9d45 Revert "Reland "[python] Bump Python minimum version to 3.8 (#78828)""
This reverts commit f2931182fc877e813974a5f53721f859bfb5b130.

This was again causing buildbot failures. #83962 has been updated with the new
failures, notifying the buildbot maintainers that they need to update their
bots.
2024-04-20 14:39:03 -07:00
Aiden Grossman
f2931182fc Reland "[python] Bump Python minimum version to 3.8 (#78828)"
This reverts commit 2dfa30d0ca6fb6991640a18e53401d82f567f8ff.

This relands commit 0a6c74e21cc6750c843310ab35b47763cddaaf32.

This patch originally caused a host of buildbot failures due to several
buildbots not having the necessary python version. That was tracked in
issue #83962, and all bots that failed in the first round have now been
updated. This is an attempt to reland the patch to see if it sticks or
if there are a number of long-running bots where this patch will cause
failures.
2024-04-20 00:49:47 +00:00