1496 Commits

Author SHA1 Message Date
Eric Christopher
fc6ffede65 Default enable the rtm feature only on skylake and later for now because Intel disabled the feature on some haswell and broadwell processors:
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/core-m-processor-family-spec-update.pdf

the -mrtm option will still work normally.

llvm-svn: 298956
2017-03-28 23:03:19 +00:00
Eric Christopher
1e6fedbb83 _CALL_LINUX is only defined on 64-bit ppc linux platforms, not 32-bit.
Adjust and add a test for the 32-bit side.

llvm-svn: 298778
2017-03-25 19:26:04 +00:00
Yaxun Liu
354097b05d [AMDGPU] Make AMDGPUTargetInfo::AS private
llvm-svn: 298773
2017-03-25 11:34:41 +00:00
Eric Christopher
19d8c1fed2 Update the comment on not yet generated preprocessor defines to remove __LONGDOUBLE128.
llvm-svn: 298771
2017-03-25 06:38:57 +00:00
Eric Christopher
ee21410bdc Add the __LONGDOUBLE128 define for ppc targets that have 128 bit long doubles.
llvm-svn: 298770
2017-03-25 06:37:23 +00:00
Eric Christopher
0d36116394 Define __HAVE_BSWAP__ on ppc to match gcc since we support both builtins as well.
llvm-svn: 298769
2017-03-25 05:40:13 +00:00
Yaxun Liu
3464f92e23 [AMDGPU] Switch address space mapping by triple environment amdgiz
For target environment amdgiz and amdgizcl (giz means Generic Is Zero), AMDGPU will use new address space mapping where generic address space is 0 and private address space is 5. The data layout is also changed correspondingly.

Differential Revision: https://reviews.llvm.org/D31210

llvm-svn: 298767
2017-03-25 03:46:25 +00:00
Eric Christopher
2fd2eda0ac Add the _CALL_LINUX preprocessor define for ppc linux platforms.
This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but
our ppc suppport post-dates this and it should work on all linux platforms. It
is guaranteed to work on all elfv2 platforms.

llvm-svn: 298765
2017-03-25 03:33:59 +00:00
Eric Christopher
153dad4ca9 __BIGGEST_ALIGNMENT__ has always been 16 on all power platforms rather
than the default of 8 in clang, fix and update tests accordingly.

llvm-svn: 298761
2017-03-25 02:55:21 +00:00
Eric Christopher
b70819e6a2 Add preprocessor defines for a bare powerpc64le triple/cpu.
The le triple didn't exist until power8, so use that as a default (this
also matches what gcc does).

llvm-svn: 298759
2017-03-25 02:29:18 +00:00
Eric Christopher
3646e6289d Move setting of LangOpts based on target flags out of CompilerInstance
and into TargetInfo::adjust so that it gets called in more places
throughout the compiler (AST serialization in particular).

Should fix PPC modules after removing of faltivec.

llvm-svn: 298487
2017-03-22 06:36:09 +00:00
Eric Christopher
758aad76d8 Remove the -faltivec alias option and replace it with -maltivec everywhere.
The alias was only ever used on darwin and had some issues there,
and isn't used in practice much. Also fixes a problem with -mno-altivec
not turning off -maltivec.

Also add a diagnostic for faltivec/fno-altivec that directs users to use
maltivec options and include the altivec.h file explicitly.

llvm-svn: 298449
2017-03-21 22:06:18 +00:00
Eric Christopher
74fa24ff27 Turn on HTM on power8 and later (including powerpc64le) since it's
available by default on those cpus and configurations.

llvm-svn: 298307
2017-03-20 21:12:53 +00:00
Krzysztof Parzyszek
ff7f6675e7 [Hexagon] Recognize hexagonv62 as a valid target CPU
llvm-svn: 297778
2017-03-14 20:29:23 +00:00
Matt Arsenault
bf5e3e4391 AMDGPU: Make 0 the private nullptr value
We can't actually pretend that 0 is valid for address space 0.
r295877 added a workaround to stop allocating user objects
there, so we can use 0 as the invalid pointer.

Some of the tests seemed to be using private as the non-0 null
test address space, so add copies using local to make sure
this is still stressed.

llvm-svn: 297659
2017-03-13 19:47:53 +00:00
Yaxun Liu
4d86799219 [AMDGPU] Add builtin functions readlane ds_permute mov_dpp
Differential Revision: https://reviews.llvm.org/D30551

llvm-svn: 297436
2017-03-10 01:30:46 +00:00
Konstantin Zhuravlyov
d1ba16e762 [DebugInfo] Add address space when creating DIDerivedTypes
Differential Revision: https://reviews.llvm.org/D29671

llvm-svn: 297321
2017-03-08 23:56:48 +00:00
Brad Smith
8e55bd5bbd Set the Int64Type / IntMaxType types correctly for OpenBSD/mips64
llvm-svn: 297098
2017-03-06 23:48:31 +00:00
Eric Christopher
fb834a8278 Migrate all of aarch64-linux-gnu to \01_mcount instead of just when passing along gnueabi as this matches both gcc and what the kernel expects.
More of PR27311

llvm-svn: 296490
2017-02-28 17:22:05 +00:00
Brad Smith
3d648b357a Set ABIs correctly for OpenBSD/arm; soft float and aapcs-linux.
llvm-svn: 296430
2017-02-28 03:20:26 +00:00
Matt Arsenault
a0c6dca15b AMDGPU: Add fmed3 half builtin
llvm-svn: 295874
2017-02-22 20:55:59 +00:00
Brad Smith
9aa2bf209b Hook up OpenBSD AArch64 support
llvm-svn: 295786
2017-02-21 23:13:09 +00:00
Simon Dardis
df827a7165 [mips] Define macros related to -mabicalls in the preprocessor
Summary:
Historically, NetBSD, FreeBSD and OpenBSD have defined the macro ABICALLS in
the preprocessor when -mabicalls is in effect.

Mainline GCC later defined __mips_abicalls when -mabicalls is in effect.

This patch teaches the preprocessor to define these macros when appropriate.

NetBSD does not require the ABICALLS macro.

This resolves PR/31694.

Thanks to Sean Bruno for highlighting this issue!

Reviewers: slthakur, seanbruno

Reviewed By: seanbruno

Subscribers: joerg, brad, emaste, seanbruno, cfe-commits

Differential Revision: https://reviews.llvm.org/D29032

llvm-svn: 295728
2017-02-21 16:01:00 +00:00
Brad Smith
0561a5a7fe Enable support for __float128 in Clang on OpenBSD/X86
/usr/local/include/c++/4.9.4/type_traits:279:39: error: __float128 is not
supported on this target

llvm-svn: 295635
2017-02-20 03:18:15 +00:00
Matt Arsenault
eb952fd93b AMDGPU: Add gfx900 and gfx901 processors
llvm-svn: 295556
2017-02-18 19:02:41 +00:00
Eric Christopher
32ac5e41ef Add a definition for __STRUCT_PARM_ALIGN__ for elfv2 and 64-bit darwin platforms to match what other compilers produce.
llvm-svn: 295156
2017-02-15 07:50:11 +00:00
Dylan McKay
315edb0216 [AVR] Fix __AVR_xxx macro definitions; authored by Peter Wu
Summary:
The -mmcu option for GCC sets macros like __AVR_ATmega328P__ (with the trailing
underscores), be sure to include these underscores for Clangs -mcpu option.

See "AVR Built-in Macros" in https://gcc.gnu.org/onlinedocs/gcc/AVR-Options.html

Reviewers: jroelofs, dylanmckay

Reviewed By: jroelofs, dylanmckay

Subscribers: efriedma, cfe-commits

Differential Revision: https://reviews.llvm.org/D29817

llvm-svn: 294869
2017-02-11 21:06:07 +00:00
Eric Christopher
f6ee1f3d69 Temporarily revert "For X86-64 linux and PPC64 linux align int128 to 16 bytes."
until we can get better TargetMachine::isCompatibleDataLayout to compare - otherwise
we can't code generate existing bitcode without a string equality data layout.

This reverts commit r294703.

llvm-svn: 294708
2017-02-10 04:35:21 +00:00
Eric Christopher
4855ba8f24 For X86-64 linux and PPC64 linux align int128 to 16 bytes.
For other platforms we should find out what they need and likely
make the same change, however, a smaller additional change is easier
for platforms we know have it specified in the ABI.

clang support for r294702

llvm-svn: 294703
2017-02-10 03:32:34 +00:00
George Burgess IV
fc9705679e Add support for armv7ve flag in clang (PR31358).
This is a followup change to add v7ve support to clang for gcc
compatibility. Please see r294661.

Patch by Manoj Gupta.

Differential Revision: https://reviews.llvm.org/D29773

llvm-svn: 294662
2017-02-09 23:30:10 +00:00
Craig Topper
4574226c3f [X86] Clzero flag addition and inclusion under znver1
1. Adds the command line flag for clzero.
2. Includes the clzero flag under znver1.
3. Defines the macro for clzero.
4. Adds a new file which has the intrinsic definition for clzero instruction.

Patch by Ganesh Gopalasubramanian with some additional tests from me.

Differential revision: https://reviews.llvm.org/D29386

llvm-svn: 294559
2017-02-09 06:10:14 +00:00
Craig Topper
d2bf7b03e5 [X86] Add -mprefetchwt1/-mno-prefetchwt1 command line options and __PREFETCHWT1__ define to match gcc.
llvm-svn: 294424
2017-02-08 08:23:40 +00:00
Craig Topper
204ecffdb4 [X86] Add -msgx/-mno-sgx command line options and __SGX__ define to match gcc.
llvm-svn: 294423
2017-02-08 08:23:17 +00:00
Craig Topper
b16cb82c93 [X86] Add -mmpx/-mno-mpx command line options and __MPX__ define to match gcc.
llvm-svn: 294419
2017-02-08 07:56:42 +00:00
Craig Topper
8c708cf6bc [X86] Add -mclwb/-mno-clwb command line arguments and __CLWB__ define to match gcc.
In the future, we should also add a clwb intrinsic to the backend, a frontend builtin, and an instrinsic header file.

llvm-svn: 294416
2017-02-08 07:36:58 +00:00
Craig Topper
32c959dab3 [X86] Remove 'umip' feature flag.
This feature flag indicates that the processor has support for removing certain instructions from user mode software. But the feature flag by itself doesn't indicate if the support is enabled in the OS. The affected instructions aren't even instructions the compiler would emit. So I don't think think this feature flag should be in the compiler.

llvm-svn: 294414
2017-02-08 07:13:22 +00:00
Craig Topper
78b4787593 [X86] Add -mclflushopt/-mno-clflushopt command line support and __CLFLUSHOPT__ define to match gcc.
llvm-svn: 294411
2017-02-08 06:48:58 +00:00
Craig Topper
7d494ef610 Use LLVM_FALLTHROUGH instead of FALLTHROUGH comments.
llvm-svn: 294404
2017-02-08 05:44:30 +00:00
Craig Topper
c31d9e4a01 [X86] Remove PCOMMIT feature support since Intel has deprecated this instruction with no plans to release products with it.
Intel's documentation for the deprecation https://software.intel.com/en-us/blogs/2016/09/12/deprecate-pcommit-instruction

llvm-svn: 294403
2017-02-08 05:44:28 +00:00
Saleem Abdulrasool
5602709b98 Revert "Basic: match GCC behaviour for SuS macro"
This reverts commit SVN r294148.  Seems that it was mistaken, and GCC
does still define `__unix` and `unix` when in GNU mode.

llvm-svn: 294332
2017-02-07 19:00:06 +00:00
Dylan McKay
ecb6e7b83c Revert "Revert "[AVR] Allow specifying the CPU on the command line""
This reverts commit 7ac30e0f839fdab6d723ce2ef6a5b7a4cf03d150.

llvm-svn: 294282
2017-02-07 06:04:18 +00:00
Ulrich Weigand
82a86cb155 [SystemZ] Provide predefined __ARCH__ and __VX__ macros
GCC 7 will predefine two new macros on s390x:

- __ARCH__ indicates the ISA architecture level
- __VX__ indicates that the vector facility is available

This adds those macros to clang as well to ensure continued
compatibility with GCC.

llvm-svn: 294197
2017-02-06 17:04:22 +00:00
Diana Picus
37a2d6d699 Revert "[AVR] Allow specifying the CPU on the command line"
This reverts commit r294177. It seems to have broken some buildbots.

llvm-svn: 294180
2017-02-06 11:35:42 +00:00
Dylan McKay
8464c9b579 [AVR] Allow specifying the CPU on the command line
Summary:
This tells clang about all of the different AVR microcontrollers.

It also adds code to define the correct preprocessor macros for each
device.

Reviewers: jroelofs, asl

Reviewed By: asl

Subscribers: asl, cfe-commits

Differential Revision: https://reviews.llvm.org/D28346

llvm-svn: 294177
2017-02-06 09:07:56 +00:00
Dylan McKay
d31534cd3a [AVR] Add support for the full set of inline asm constraints
Summary:
Previously the method would simply return false, causing every single
inline assembly constraint to trigger a compile error.

This adds inline assembly constraint support for the AVR target.

This patch is derived from the code in
AVRISelLowering::getConstraintType.

More details can be found on the AVR-GCC reference wiki
http://www.nongnu.org/avr-libc/user-manual/inline_asm.html

Reviewers: jroelofs, asl

Reviewed By: asl

Subscribers: asl, ahatanak, saaadhu, cfe-commits

Differential Revision: https://reviews.llvm.org/D28344

llvm-svn: 294176
2017-02-06 09:01:59 +00:00
Saleem Abdulrasool
c5cddc9fa8 Basic: match GCC behaviour for SuS macro
GCC does not generate `__unix` nor `unix` macros.  The latter already
intrudes into the user's namespace and should be avoided.  Use the
canonical spelling of `__unix__` across all the targets.

llvm-svn: 294148
2017-02-05 22:18:15 +00:00
Matt Arsenault
09cca093a3 AMDGPU: Update for changed subtarget feature name
llvm-svn: 292838
2017-01-23 22:31:14 +00:00
Petr Hosek
8c69cffe15 [Basic] Remove the 32-bit x86 and ARM targets for Fuchsia
The 32-bit architectures are no longer supported by Fuchsia.

Differential Revision: https://reviews.llvm.org/D28974

llvm-svn: 292671
2017-01-20 22:53:38 +00:00
Dan Gohman
839f215e19 [WebAssembly] Add minimal support for the new wasm object format triple.
llvm-svn: 292269
2017-01-17 21:46:38 +00:00
Joerg Sonnenberger
8450266425 Ensure that clang -pthread creates the right macro. -D_POSIX_THREADS
seems to have been a C&P error from old GCC specs for OpenBSD.

llvm-svn: 292119
2017-01-16 14:07:24 +00:00