533919 Commits

Author SHA1 Message Date
Ryosuke Niwa
c26d097d0c
[alpha.webkit.RetainPtrCtorAdoptChecker] Support adopt(cast(copy(~)) (#132316)
This PR adds the support for recognizing calling adoptCF/adoptNS on the
result of a cast operation on the return value of a function which
creates NS or CF types. It also fixes a bug that we weren't reporting
memory leaks when CF types are created without ever calling RetainPtr's
constructor, adoptCF, or adoptNS.

To do this, this PR adds a new mechanism to report a memory leak
whenever create or copy CF functions are invoked unless this CallExpr
has already been visited while validating a call to adoptCF. Also added
an early exit when isOwned returns IsOwnedResult::Skip due to an
unresolved template argument.
2025-04-10 15:26:10 -07:00
Ulrich Weigand
80267f8148
Support z17 processor name and scheduler description (#135254)
The recently announced IBM z17 processor implements the architecture
already supported as "arch15" in LLVM. This patch adds support for "z17"
as an alternate architecture name for arch15.

This patch also add the scheduler description for the z17 processor,
provided by Jonas Paulsson.
2025-04-11 00:20:58 +02:00
Thurston Dang
324083b5fe [asan] Fix-forward #133175 by avoiding designated initializers
My patch broke the Windows build:

C:\PROGRA~2\MIB055~1\2019\PROFES~1\VC\Tools\MSVC\1429~1.301\bin\Hostx64\x64\cl.exe  /nologo /TP -DASAN_DYNAMIC=1 -DINTERCEPTION_DYNAMIC_CRT -DUNICODE -D_CRT_NONSTDC_NO_DEPRECATE -D_CRT_NONSTDC_NO_WARNINGS -D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS -D_GLIBCXX_ASSERTIONS -D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS -D_UNICODE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -IC:\b\slave\sanitizer-windows\build\stage1\projects\compiler-rt\lib\asan -IC:\b\slave\sanitizer-windows\llvm-project\compiler-rt\lib\asan -IC:\b\slave\sanitizer-windows\build\stage1\include -IC:\b\slave\sanitizer-windows\llvm-project\llvm\include -IC:\b\slave\sanitizer-windows\llvm-project\compiler-rt\lib\asan\.. /DWIN32 /D_WINDOWS   /Zc:inline /Zc:preprocessor /Zc:__cplusplus /Z7 /Oi /bigobj /permissive- -wd4141 -wd4146 -wd4244 -wd4267 -wd4291 -wd4351 -wd4456 -wd4457 -wd4458 -wd4459 -wd4503 -wd4624 -wd4722 -wd4100 -wd4127 -wd4512 -wd4505 -wd4610 -wd4510 -wd4702 -wd4245 -wd4706 -wd4310 -wd4701 -wd4703 -wd4389 -wd4611 -wd4805 -wd4204 -wd4577 -wd4091 -wd4592 -wd4319 -wd4709 -wd5105 -wd4324 -wd4251 -wd4275 -w14062 -we4238 /Gw /W4 /O2 /Ob2  -std:c++17 -MD /Oy- /GS- /Zc:threadSafeInit- /Z7 /wd4146 /wd4291 /wd4391 /wd4722 /wd4800 /Zl /GR- /experimental:external /external:W0 /external:anglebrackets /showIncludes /Foprojects\compiler-rt\lib\asan\CMakeFiles\RTAsan_dynamic.x86_64.dir\asan_poisoning.cpp.obj /Fdprojects\compiler-rt\lib\asan\CMakeFiles\RTAsan_dynamic.x86_64.dir\ /FS -c C:\b\slave\sanitizer-windows\llvm-project\compiler-rt\lib\asan\asan_poisoning.cpp
C:\b\slave\sanitizer-windows\llvm-project\compiler-rt\lib\asan\asan_poisoning.cpp(164): error C7555: use of designated initializers requires at least '/std:c++20'
[2/3] Building CXX object projects\compiler-rt\lib\asan\CMakeFiles\RTAsan_dynamic_version_script_dummy.x86_64.dir\dummy.cpp.obj

https://lab.llvm.org/buildbot/#/builders/107/builds/9712/steps/4/logs/stdio
2025-04-10 22:19:13 +00:00
Amr Hesham
78921cd884
[CIR] Upstream ArraySubscriptExpr for fixed size array (#134536)
This change adds ArraySubscriptExpr for fixed size ArrayType

Issue #130197
2025-04-11 00:05:22 +02:00
erichkeane
2667845484 [OpenACC] device_type on set should have only 1 architecture
Discussions with the OpenACC Standard folks and the dialect folks showed
that the ability to have 'set' have a 'device_type' with more than one
architecture was a mistake, and one that will be fixed in future
revisions of the standard.  Since the dialect requires this anyway,
we'll implement this in advance of standardization.
2025-04-10 14:49:13 -07:00
Jeffrey Byrnes
5de3118c67
[AMDGPU] Make the iterative schedulers selectable via amdgpu-sched-strategy (#135042)
Currently, the only way for users to try these schedulers is via
`-misched=` . However, this overrides the default scheduler for all
targets. This causes problems for various toolchains / drivers which
spawn jobs for both x86 and AMDGPU -- e.g. hipcc. On the other hand,
`amdgpu-sched-strategy` only changes the scheduler for AMDGPU target.
2025-04-10 14:43:42 -07:00
Philip Reames
01ee922b2a [RISCV] Add coverage for missing vrgather.vi shuffle case
If we have a near identity shuffle with a single element repeated, we
manage to match this as a masked vrgather.vi for the two operand
forms, but not the single operand form.  If the scalar being repeated
was a scalar just inserted into the vector, we're also missing a
chance to recognize a vmerge.vxm or vmerge.vim in both cases.
2025-04-10 14:42:11 -07:00
Florian Hahn
6a9e8fc50c
[VPlan] Introduce VPInstructionWithType, use instead of VPScalarCast(NFC) (#129706)
There are some opcodes that currently require specialized recipes, due
to their result type not being implied by their operands, including
casts.

This leads to duplication from defining multiple full recipes.

This patch introduces a new VPInstructionWithType subclass that also
stores the result type. The general idea is to have opcodes needing to
specify a result type to use this general recipe. The current patch
replaces VPScalarCastRecipe with VInstructionWithType, a similar patch
for VPWidenCastRecipe will follow soon.

There are a few proposed opcodes that should also benefit, without the
need of workarounds:
* https://github.com/llvm/llvm-project/pull/129508
* https://github.com/llvm/llvm-project/pull/119284

PR: https://github.com/llvm/llvm-project/pull/129706
2025-04-10 22:30:40 +01:00
mojyack
801b519dfd
[sanitizer_common] Fix build on ppc64+musl (#120036)
In powerpc64-unknown-linux-musl, signal.h does not include asm/ptrace.h,
which causes "member access into incomplete type 'struct pt_regs'"
errors. Include the header explicitly to fix this.

Also in sanitizer_linux_libcdep.cpp, there is a usage of TlsPreTcbSize
which is not defined in such a platform. Guard the branch with macro.
2025-04-10 14:23:26 -07:00
jeremyd2019
e4a79b7122
[LLD] [MinGW] Fall back to using default target if no -m flag given. (#134700)
On Cygwin at least, GCC is not passing any -m flag to the linker, so
fall back to the default target triple to determine if we need to apply
i386-specific behaviors.

Fixes #134558
2025-04-11 00:20:10 +03:00
Andy Kaylor
db22909089
[CIR] Upstream support for cir.get_global (#135095)
This adds basic support for referencing global variables from within
functions via the cir.get_global operation.
2025-04-10 14:15:10 -07:00
Pengxuan Zheng
36acaa0be5 Revert "[ARM][ConstantIslands] Correct MinNoSplitDisp calculation (#114590)"
This reverts commit e48916f615e0ad2b994b2b785d4fe1b8a98bc322.
2025-04-10 13:56:52 -07:00
Thurston Dang
721af7e636
[asan] Add experimental 'poison_history_size' flag (#133175)
This adds an experimental flag that will keep track of where the manual memory poisoning (`__asan_poison_memory_region`) is called from, and print the stack trace if the poisoned region is accessed. (Absent this flag, ASan will tell you what code accessed a poisoned region, but not which code set the poison.)

This implementation performs best-effort record keeping using ring buffers, as suggested by Vitaly. The size of each ring buffer is set by the `poison_history_size` flag.
2025-04-10 13:53:54 -07:00
Valentin Clement (バレンタイン クレメン)
49f8ccd1eb
[flang][cuda] Pass stream information to kernel launch functions (#135246) 2025-04-10 13:50:50 -07:00
Farzon Lotfi
641de84d3b
[DirectX] legalize powi (#135228)
fixes #135221
- have powi use the same legalization path as pow
- use CreateSIToFP to cast the int back to a float type
- add tests for powi
2025-04-10 16:40:05 -04:00
zhijian lin
5aeeebc1f4
[NFC] add a pre-commit test case for patch 122741 (#135247)
[NFC] add a pre-commit test case for patch [Eliminating li of 0 into arg
registers of unused
arguments](https://github.com/llvm/llvm-project/pull/122741)

The test case tests that extend poison are lower to undef and also test
there are redendunt instrution load 0 into argument registers for unused
arguments.
2025-04-10 16:33:40 -04:00
Matt Arsenault
a80a802d2f
IROutliner: Use ValueMapper to remap constants in a function (#134850)
Stop relying on the uselist of constants, which also required filtering
the uses that are in the correct function. I'm not sure why this pass is
doing its own cloning instead of building the value map while doing its
cloning.
2025-04-10 22:31:02 +02:00
alex-t
edd7b559c0
Reapply [AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#135243)
LIT tests which were incorrectly merged are corrected.
2025-04-10 22:18:21 +02:00
tltao
18189430ab
[SystemZ] Add check for INIT_UNDEF in getInstSizeInBytes (#134661)
Due to some optimization changes, INIT_UNDEF is making its way to
`getInstSizeInBytes` in `llvm/lib/Target/SystemZ/SystemZLongBranch.cpp`
but we do not have an exception there in the assert. Since INIT_UNDEF is
described as being similar to IMPLICIT_DEF and there is a check for
IMPLICIT_DEF, it seems logical to also add a check for INIT_UNDEF.

---------

Co-authored-by: Tony Tao <tonytao@ca.ibm.com>
2025-04-10 16:16:20 -04:00
Aiden Grossman
ed4c397908
[Github] Bump workflows depending on CI container to ubuntu 24.04 (#133626)
This patch bumps workflows depending upon the Linux CI container to
ubuntu 24.04. The 22.04 container is no longer being built as it was
recently bumped to 24.04, so this patch moves all of these workflows
over to the new container to keep them updated and ensure they are using
an actually maintained version of the container image.
2025-04-10 13:13:50 -07:00
Alexey Bataev
61d04f1aac
[SLP][NFC]Extract preliminary checks from buildTree_rec, NFC
Moved check from buildTree_rec function to a separate
isLegalToVectorizeScalars function.

Reviewers: RKSimon, hiraditya

Reviewed By: RKSimon

Pull Request: https://github.com/llvm/llvm-project/pull/134132
2025-04-10 16:05:01 -04:00
David Green
e762baffd9 [AArch64] Move SLId/SRId patterns into instruction definitions. NFC
The v1i64 patterns were next to the vector variants, not the SIMDScalar
instructions tht define them. In moving them closer they cal also be
incorporated into the definitions themselves. SIMDScalarRShiftDTied is
altered to remove the redundant i64 variants.
2025-04-10 20:57:53 +01:00
Ashley Coleman
966667f541
[NFC][HLSL] Refactor DXILResourceTest for upcoming PR (#134952)
Local changes were getting pretty large and complex so this is an NFC
refactor PR to simplify the upcoming changes
2025-04-10 13:56:34 -06:00
darkbuck
9188288581
[mlir][DataLayout] Keep consistent input/output order (#135185)
- Use 'MapVector' instead of 'DenseMap' to keep a consistent order when
importing/printing entries to prevent run-by-run differences.
2025-04-10 15:55:37 -04:00
Matthias Springer
53ae2bdceb
[mlir][NVVM] Remove commented out code (#135144)
This addresses a comment on #135051.
2025-04-10 21:51:32 +02:00
Pranav Kant
a1bca4ba37
[clang] Make tests write to /dev/null if output is not needed (#135242)
We execute tests in read only environment which leads to test failure
when tests try to write to the current directory. Either they should
write to a temporary directory or not write if output is not needed.

Fallback from #134717
2025-04-10 12:50:05 -07:00
Erich Keane
74c2b41feb
[OpenACC][CIR] Implement 'device_type' clause lowering for 'init'/'sh… (#135102)
…utdown'

This patch emits the lowering for 'device_type' on an 'init' or
'shutdown'. This one is fairly unique, as these directives have it as an
attribute, rather than as a component of the individual operands, like
the rest of the constructs.

So this patch implements the lowering as an attribute.

In order to do tis, a few refactorings had to happen: First, the
'emitOpenACCOp' functions needed to pick up th edirective kind/location
so that the NYI diagnostic could be reasonable.

Second, and most impactful, the `applyAttributes` function ends up
needing to encode some of the appertainment rules, thanks to the way the
OpenACC-MLIR operands get their attributes attached. Since they each use
a special function (rather than something that can be legalized at
runtime), the forms of 'setDefaultAttr' is only valid for some ops. SO
this patch uses some `if constexpr` and a small type-trait to help
legalize these.
2025-04-10 12:38:35 -07:00
Jan Svoboda
dcb9078081
[clang][index] Skip over #include UNDEF_IDENT in single-file-parse mode (#135218)
In the 'single-file-parse' mode, seeing `#include UNDEFINED_IDENTIFIER`
should not be treated as an error. The identifier might be defined in a
header that we decided to skip, resulting in a nonsensical diagnostic
from the user point of view.
2025-04-10 12:32:01 -07:00
Andreas Jonson
72436b37bf [InstCombine] add more test for #134712 (NFC) 2025-04-10 21:28:49 +02:00
Guray Ozen
d7cb24e10d
[MLIR][NVVM] Run clang-tidy (#135006) 2025-04-10 21:12:14 +02:00
Drew Lewis
d07a2164e7
Add generic sqrt root headers to libc sqrt specializations (#135237)
This header is needed to provide the declaration for the sqrt template.
You can build without these in the CMake build, but not having this
include in the architecture specific headers makes them not self
contained.
2025-04-10 12:04:41 -07:00
Nicolai Hähnle
9c31155ead
TableGen: Optimize super-register class computation (#134865)
Inferring super-register classes naively requires checking every
register class against every other register class and sub-register
index.
Each of those checks is itself a non-trivial operation on register sets.

Culling as many (RC, RC, SubIdx) triples as possible is important for
the running time of TableGen for architectures with complex sub-register
relations.

Use transitivity to cull many (RC, RC, SubIdx) triples. This
unfortunately requires us to complete the transitive closure of
super-register classes explicitly, but it still cuts down the running
time on AMDGPU substantially -- in some upcoming work in the
backend by more than half (in very rough measurements).

This changes the names of some of the inferred register classes, since
the order in which they are inferred changes. The names of the inferred
register classes become shorter, which reduces the size of the generated
files.

Replacing some uses of SmallPtrSet by DenseSet shaves off a few more
percent; there are hundreds of register classes in AMDGPU.

Tweaking the topological signature check to skip reigsters without
super-registers further helps skip register classes that have "pseudo"
registers in them whose sub- and super-register structure is trivial.
2025-04-10 12:00:08 -07:00
Valentin Clement (バレンタイン クレメン)
ca53463137
[flang][cuda] Propagate stream information to gpu.launch_func op (#135227)
Use the information from `cuf.kernel_launch` to `gpu.launch_func`
2025-04-10 11:58:18 -07:00
Tai Ly
ccdbd3b78d
[mlir][tosa] Rename int_div to intdiv (#135080)
This patch renames Tosa Operator int_div to intdiv to align with 1.0
spec

Signed-off-by: Tai Ly <tai.ly@arm.com>
2025-04-10 11:54:34 -07:00
Pranav Kant
22c3dac454
[bazel] Fix for #134956 (#135233) 2025-04-10 11:52:33 -07:00
Tim Clephas
c893f1d18d
Treat ipynb as json (#135137)
Fixes #110727
2025-04-10 20:40:43 +02:00
Leonard Grey
8bea91f677
[lld-macho] Support archives without index (#132942)
This is a ~port of https://reviews.llvm.org/D117284. Like in that
change, archives without indices are treated as a collection of lazy
object files (as in `--start-lib/--end-lib`)

Porting the ELF follow-up to convert *all* archives to the lazy object
code path (https://reviews.llvm.org/D119074) is a natural next step, but
we would need to ensure the assertions about memory use hold for Mach-O.

NB: without an index, we can't do the part of the `-ObjC` scan where we
check for Objective-C symbols directly. We *can* still check for
`__obcj` sections so I wonder how much of a problem this actually is,
since I'm not sure how the "symbols but no sections" case can appear in
the wild.
2025-04-10 14:33:56 -04:00
Farzon Lotfi
589e1c73d0
[HLSL] Add support for modulo of floating point scalar and vectors (#135125)
fixes #135122

SemaExpr.cpp - Make all doubles fail. Add sema support for float scalars
and vectors when language mode is HLSL.
CGExprScalar.cpp - Allow emit frem when language mode is HLSL.
2025-04-10 14:27:49 -04:00
Slava Zakharin
755016a3a8
[flang-rt] Fixed warnings and miscompilations in CUDA build. (#134470)
* DescribeIEEESignaledExceptions() is unused on the device - warning.
* StopStatementText() could return while marked noreturn - warning.
* Including cuda/std/complex only in the device compilation
  may cause nvcc to try to register variables in `cuda` namespace,
  while they are not defined in the host compilation - error.
  I decided to include cuda/std/complex always under RT_USE_LIBCUDACXX.
2025-04-10 11:27:03 -07:00
Justin Lebar
337a4d5526
[NVPTX] Use sink registers instead of temp registers where possible. (#134957)
PTX 7.1 introduces the concept of a "sink" register, `_`, which is a
register to which writes are ignored.

This patch makes us use sink registers where possible, instead of using
explicit temp registers.

This results in cleaner assembly, and also works around a problem we
encountered in some private workloads.

(Unfortunately the tablegen is not particularly clean. But then again,
it's tablegen...)
2025-04-10 11:13:33 -07:00
Valentin Clement (バレンタイン クレメン)
6ca9a30c26
[flang][cuda] Update stream operand type for cuf.kernel_launch op (#135222) 2025-04-10 11:13:27 -07:00
Jonas Devlieghere
6493345c5a
[lldb] Handle signals in a separate thread in the driver (#134956)
Handle signals in a separate thread in the driver so that we can stop
worrying about signal safety of functions in libLLDB that may get called
from a signal handler.
2025-04-10 11:04:05 -07:00
Malavika Samak
9102ccd2f7
[CXX Safe Buffer] Update the documentation for unsafe_buffer_usage attribute (#135087)
Update the documentation for the unsafe_buffer_usage attribute to
capture the new behavior introduced by
https://github.com/llvm/llvm-project/pull/125671

Co-authored-by: MalavikaSamak <malavika2@apple.com>
2025-04-10 11:00:02 -07:00
Anatoly Trosinenko
2927050dd4
[BOLT] Gadget scanner: refine class names and debug output (NFC) (#135073)
Scanning functions without CFG information as well as the detection of
authentication oracles requires introducing more classes related to
register state analysis. To make the future code easier to understand,
rename several classes beforehand.

To detect authentication oracles, one has to query the properties of
*output* operands of authentication instructions *after* the instruction
is executed - this requires adding another analysis that iterates over
the instructions in reverse order, and a corresponding state class.

As the main difference of the existing `State` class is that it stores
the properties of source register operands of the instructions before
the instruction's execution, rename it to `SrcState` and
`PacRetAnalysis` to `SrcSafetyAnalysis`.

Apply minor adjustments to the debug output along the way.
2025-04-10 20:54:05 +03:00
Peter Klausler
cd56666d7b
[flang][runtime] Fix CUDA flang-rt build breakage (#135220)
I used "std::nullopt" instead of the correct "Fortran::common::nullopt"
in a recent patch, and you can get away with that only for CPU builds.
Fix.
2025-04-10 10:39:27 -07:00
Peter Collingbourne
f53eb88d25
ELF: Remove lock from MTE global relocation handling code.
This lock is unnecessary because we can add the relocations to
shards and let them be sorted later.

Reviewers: smithp35, fmayer, MaskRay

Reviewed By: MaskRay

Pull Request: https://github.com/llvm/llvm-project/pull/135123
2025-04-10 10:38:59 -07:00
Peter Collingbourne
a4e6a771a6
libcxx: In gdb test detect execute_mi with feature check instead of version check.
The existing version check can lead to test failures on some distribution
packages of gdb where not all components of the version number are
integers, such as Fedora where gdb.VERSION can be something like
"15.2-4.fc41". Fix it by replacing the version check with a feature check.

Reviewers: philnik777

Reviewed By: philnik777

Pull Request: https://github.com/llvm/llvm-project/pull/132291
2025-04-10 10:38:08 -07:00
Andreas Jonson
39562de510
[ValueTracking] Handle assume(trunc x to i1) in ComputeKnownBits (#118406)
proof: https://alive2.llvm.org/ce/z/zAspzb
2025-04-10 19:29:28 +02:00
Matheus Izvekov
3954d258a5
[clang] Improved canonicalization for template specialization types (#135119)
This changes the TemplateArgument representation to hold a flag
indicating whether a template argument of expression type is supposed to
be canonical or not.

This gets one step closer to solving
https://github.com/llvm/llvm-project/issues/92292

This still doesn't try to unique as-written TSTs. While this would
increase the amount of memory savings and make code dealing with the AST
more well-behaved, profiling template argument lists is still too
expensive for this to be worthwhile, at least for now. Without this
uniquing, this patch stands neutral in terms of performance impact.

This also fixes the context creation of TSTs, so that they don't in some
cases get incorrectly flagged as sugar over their own canonical form.
This is captured in the test expectation change of some AST dumps.

This fixes some places which were unnecessarily canonicalizing these
TSTs.
2025-04-10 14:23:02 -03:00
Nico Weber
464035fc7d Revert "[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. (#134153)"
This reverts commit 0563569978fee1e780a560494c89869074933f58.

Breaks tests, see comments on https://github.com/llvm/llvm-project/pull/134153
2025-04-10 13:20:01 -04:00