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329 Commits

Author SHA1 Message Date
Dale Johannesen
446b900192 Add mod, copysign, abs operations to APFloat. 
Implement some constant folding in SelectionDAG and
DAGCombiner using APFloat.  Remove double versions
of constructor and getValue from ConstantFPSDNode.

llvm-svn: 41664
 2007-08-31 23:34:27 +00:00
Dan Gohman
9625d812c9 Make DAGCombiner's global alias analysis query more precise in the case 
where both pointers have non-zero offsets.

llvm-svn: 41491
 2007-08-27 16:32:11 +00:00
Dale Johannesen
b6d2bec418 Revise per review comments. 
llvm-svn: 41409
 2007-08-26 01:18:27 +00:00
Dale Johannesen
2cfcf70f82 Add APFloat interface to ConstantFPSDNode. Change 
over uses in DAGCombiner.  Fix interfaces to work
with APFloats.

llvm-svn: 41407
 2007-08-25 22:10:57 +00:00
Evan Cheng
f5a23abf37 Fold C ? 0 : 1 to ~C or zext(~C) or trunc(~C) depending the types. 
llvm-svn: 41163
 2007-08-18 05:57:05 +00:00
Dan Gohman
30f060be80 Fix the alias analysis query in DAGCombiner to not add in two 
offsets. The SrcValueOffset values are the real offsets from the
SrcValue base pointers.

llvm-svn: 40534
 2007-07-26 16:14:06 +00:00
Dan Gohman
80f9f077e3 Don't call SimplifyVBinOp for non-vector operations, following earlier review 
feedback. This theoretically makes the common (scalar) case more efficient.

llvm-svn: 39823
 2007-07-13 20:03:40 +00:00
Dan Gohman
adb3d37c07 Fix a bug in the folding of binary operators to undef. 
Thanks to Lauro for spotting this!

llvm-svn: 38491
 2007-07-10 15:19:29 +00:00
Dan Gohman
fa91282dbf Fix the folding of undef in several binary operators to recognize 
undef in either the left or right operand.

llvm-svn: 38489
 2007-07-10 14:20:37 +00:00
Dan Gohman
2af3063337 Preserve volatililty and alignment information when lowering or 
simplifying loads and stores.

llvm-svn: 38473
 2007-07-09 22:18:38 +00:00
Chris Lattner
6caf8fdd04 Fix this warning: 
DAGCombiner.cpp: In member function 'llvm::SDOperand<unnamed>::DAGCombiner::visitOR(llvm::SDNode*)':
DAGCombiner.cpp:1608: warning: passing negative value '-0x00000000000000001' for argument 1 to 'llvm::SDOperand llvm::SelectionDAG::getConstant(uint64_t, llvm::MVT::ValueType, bool)'

oiy.

llvm-svn: 38458
 2007-07-09 16:16:34 +00:00
Dan Gohman
06563a8702 Fix several over-aggressive folds for undef nodes in dagcombine, to 
follow the rules for undef used in instcombine.

llvm-svn: 37851
 2007-07-03 14:03:57 +00:00
Dan Gohman
9a70823375 Teach GetNegatedExpression to negate 0-B to B in UnsafeFPMath mode, and 
visitFSUB to fold 0-B to -B in UnsafeFPMath mode. Also change visitFNEG
to use isNegatibleForFree/GetNegatedExpression instead of doing a subset
of the same thing manually.

This fixes test/CodeGen/X86/negative-sin.ll.

llvm-svn: 37842
 2007-07-02 15:48:56 +00:00
Dan Gohman
a866514528 Generalize MVT::ValueType and associated functions to be able to represent 
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
 2007-06-25 16:23:39 +00:00
Dan Gohman
309d3d51b3 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from 
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
 2007-06-22 14:59:07 +00:00
Evan Cheng
aa5f5d960d Xforms: 
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))

llvm-svn: 37685
 2007-06-21 07:39:16 +00:00
Dan Gohman
a7644dd9b9 Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration 
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.

llvm-svn: 37656
 2007-06-19 14:13:56 +00:00
Dan Gohman
5c4413120f Rename MVT::getVectorBaseType to MVT::getVectorElementType. 
llvm-svn: 37579
 2007-06-14 22:58:02 +00:00
Chris Lattner
4698083b96 tighten up recursion depth again 
llvm-svn: 37330
 2007-05-25 02:19:06 +00:00
Evan Cheng
a4d187b8ce Fix a typo that caused combiner to create mal-formed pre-indexed store where value store is the same as the base pointer. 
llvm-svn: 37318
 2007-05-24 02:35:39 +00:00
Chris Lattner
6509c0673f prevent exponential recursion in isNegatibleForFree 
llvm-svn: 37310
 2007-05-23 07:35:22 +00:00
Dan Gohman
b539df3389 Qualify calls to getTypeForValueType with MVT:: too. 
llvm-svn: 37233
 2007-05-18 18:41:29 +00:00
Dale Johannesen
7a6c175e7a Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores. 
llvm-svn: 37130
 2007-05-16 22:45:30 +00:00
Chris Lattner
48fb92f75d Use a ptr set instead of a linear search to unique TokenFactor operands. 
This fixes PR1423

llvm-svn: 37102
 2007-05-16 06:37:59 +00:00
Evan Cheng
288f133c71 Bug fix: should check ABI alignment, not pref. alignment. 
llvm-svn: 37094
 2007-05-16 02:04:50 +00:00
Lauro Ramos Venancio
3f142cbca2 Fix an infinite recursion in GetNegatedExpression. 
llvm-svn: 37086
 2007-05-15 17:05:43 +00:00
Chris Lattner
e49c974a7c implement a simple fneg optimization/propagation thing. This compiles: 
CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054
 2007-05-14 22:04:50 +00:00
Evan Cheng
f325c2a65e Can't fold the bit_convert is the store is a truncating store. 
llvm-svn: 36962
 2007-05-09 21:49:47 +00:00
Evan Cheng
562e45692e Forgot a check. 
llvm-svn: 36910
 2007-05-07 21:36:06 +00:00
Evan Cheng
a4cf58a103 Enable a couple of xforms: 
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment

llvm-svn: 36908
 2007-05-07 21:27:48 +00:00
Evan Cheng
044a0a8cfb Don't create indexed load / store with zero offset! 
llvm-svn: 36716
 2007-05-03 23:52:19 +00:00
Evan Cheng
b68343cdd8 Forgot about chain result; also UNDEF cannot have multiple values. 
llvm-svn: 36622
 2007-05-01 08:53:39 +00:00
Evan Cheng
a684cd23a5 * Only turn a load to UNDEF if all of its outputs have no uses (indexed loads 
produce two results.)
* Do not touch volatile loads.

llvm-svn: 36604
 2007-05-01 00:38:21 +00:00
Christopher Lamb
8af6d5896f PR400 phase 2. Propagate attributed load/store information through DAGs. 
llvm-svn: 36356
 2007-04-22 23:15:30 +00:00
Reid Spencer
0c1349e6bc Revert Christopher Lamb's load/store alignment changes. 
llvm-svn: 36309
 2007-04-21 18:36:27 +00:00
Christopher Lamb
bff50208c8 add support for alignment attributes on load/store instructions 
llvm-svn: 36301
 2007-04-21 08:16:25 +00:00
Chris Lattner
f03c90bee6 allow SRL to simplify its operands, as it doesn't demand all bits as input. 
llvm-svn: 36245
 2007-04-18 03:06:49 +00:00
Chris Lattner
bf14f20632 When replacing a node in SimplifyDemandedBits, if the old node used any 
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
 2007-04-18 03:05:22 +00:00
Chris Lattner
9ad5915559 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
 2007-04-17 19:03:21 +00:00
Chris Lattner
18e4ac4107 fix an infinite loop compiling ldecod, notice by JeffC. 
llvm-svn: 35910
 2007-04-11 16:51:53 +00:00
Chris Lattner
a083ffcad7 Fix this harder. 
llvm-svn: 35888
 2007-04-11 06:50:51 +00:00
Chris Lattner
c5f85d3738 don't create shifts by zero, fix some problems with my previous patch 
llvm-svn: 35887
 2007-04-11 06:43:25 +00:00
Chris Lattner
65786b078c Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often 
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
 2007-04-11 05:32:27 +00:00
Chris Lattner
41189c63cc Codegen integer abs more efficiently using the trick from the PPC CWG. This 
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
 2007-04-11 05:11:38 +00:00
Scott Michel
16627a542f 1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL. 
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.

llvm-svn: 35605
 2007-04-02 21:36:32 +00:00
Dale Johannesen
4bbd2eefba Fix incorrect combination of different loads. Reenable zext-over-truncate 
combination.

llvm-svn: 35517
 2007-03-30 21:38:07 +00:00
Evan Cheng
ccee35fd0d Disable load width reduction xform of variant (zext (truncate load x)) for 
big endian targets until llvm-gcc build issue has been resolved.

llvm-svn: 35449
 2007-03-29 07:56:46 +00:00
Evan Cheng
8275f0e0af SIGN_EXTEND_INREG requires one extra operand, a ValueType node. 
llvm-svn: 35350
 2007-03-26 07:12:51 +00:00
Evan Cheng
b7051f596a Adjust offset to compensate for big endian machines. 
llvm-svn: 35293
 2007-03-24 00:02:43 +00:00
Evan Cheng
a883b58caf Make sure SEXTLOAD of the specific type is supported on the target. 
llvm-svn: 35289
 2007-03-23 22:13:36 +00:00