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328 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
7d7f604321 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
 2010-05-21 20:02:01 +00:00
Jakob Stoklund Olesen
b4e1687270 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
8e8e090301 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
1f3801062d If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
 2010-05-21 16:32:16 +00:00
Jakob Stoklund Olesen
5d4c134a94 Add MachineInstr::readsVirtualRegister() in preparation for proper handling of 
partial redefines.

We are going to treat a partial redefine of a virtual register as a
read-modify-write:

  %reg1024:6 = OP

Unless the register is fully clobbered:

  %reg1024:6 = OP, %reg1024<imp-def>

MachineInstr::readsVirtualRegister() knows the difference. The first case is a
read, the second isn't.

llvm-svn: 104149
 2010-05-19 20:36:22 +00:00
Dan Gohman
c90f51c00b Teach MachineLICM and MachineSink how to clear kill flags conservatively 
when they move instructions.

llvm-svn: 103737
 2010-05-13 20:34:42 +00:00
Evan Cheng
d4d1a51895 Pretty print DBG_VALUE machine instructions. 
Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707

llvm-svn: 102518
 2010-04-28 20:03:13 +00:00
Bob Wilson
d8eeb12120 Use getNumImplicitDefs() and getNumImplicitUses(). 
llvm-svn: 100850
 2010-04-09 04:46:43 +00:00
Bob Wilson
406f270148 Fix up some comments. 
llvm-svn: 100849
 2010-04-09 04:34:03 +00:00
Evan Cheng
b083c47c21 Coalescer should not delete copy instructions whose defs are partially dead. e.g. 
%RDI<def,dead> = MOV64rr %RAX<kill>, %EDI<imp-def>

llvm-svn: 100804
 2010-04-08 20:02:37 +00:00
Chris Lattner
f839ee0c13 fix a latent bug my inline asm stuff exposed: 
MachineOperand::isIdenticalTo wasn't handling metadata operands.

llvm-svn: 100636
 2010-04-07 18:03:19 +00:00
Chris Lattner
bd009d6d6d stop using DebugLoc::getUnknownLoc() 
llvm-svn: 100215
 2010-04-02 20:17:23 +00:00
Chris Lattner
915c5f9862 Switch the code generator (except the JIT) onto the new DebugLoc 
representation.  This eliminates the 'DILocation' MDNodes for 
file/line/col tuples from -O0 -g codegen.

This remove the old DebugLoc class, making it a typedef for DebugLoc,
I'll rename NewDebugLoc next.

I didn't update the JIT to use the new apis, so it will continue to
work, but be as slow as before.  Someone should eventually do this
or, better yet, rip out the JIT debug info stuff and build the JIT
on top of MC.

llvm-svn: 100209
 2010-04-02 19:42:39 +00:00
Chris Lattner
6c604e3f94 add support for MCSymbols as operands to MachineInstrs. 
llvm-svn: 98433
 2010-03-13 08:14:18 +00:00
Devang Patel
3b548aa8e2 Avoid using DIDescriptor.isNull(). 
This is a first step towards eliminating checks in Descriptor constructors.

llvm-svn: 97975
 2010-03-08 20:52:55 +00:00
Devang Patel
bc97f6b757 Revert r97947. 
llvm-svn: 97963
 2010-03-08 19:20:38 +00:00
Devang Patel
fe28599f6f Avoid using DIDescriptor.isNull(). 
This is a first step towards eliminating unncessary constructor checks in light weight DIDescriptor wrappers.

llvm-svn: 97947
 2010-03-08 18:25:48 +00:00
Evan Cheng
59d27fe597 Move MachineInstrExpressionTrait::getHashValue() out of line so it can skip over only virtual register defs. This matches what isEqual() is doing. 
llvm-svn: 97680
 2010-03-03 23:37:30 +00:00
Evan Cheng
0f260e1785 Fix funky indentation and add comments. 
llvm-svn: 97670
 2010-03-03 21:54:14 +00:00
Evan Cheng
e9c46c25a1 - Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. 
- Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools).

llvm-svn: 97628
 2010-03-03 01:44:33 +00:00
Evan Cheng
62e795ab8c Swap parameters of isSafeToMove and isSafeToReMat for consistency. 
llvm-svn: 97578
 2010-03-02 19:03:01 +00:00
David Greene
3a0412f122 Add non-temporal flags to MachineMemOperand. 
llvm-svn: 96226
 2010-02-15 16:48:31 +00:00
Dan Gohman
4a618827de Fix "the the" and similar typos. 
llvm-svn: 95781
 2010-02-10 16:03:48 +00:00
Dale Johannesen
d40d42c9e5 Add isDebug argument to ChangeToRegister; this prevents 
the field from being used uninitialized later in some cases.

llvm-svn: 95735
 2010-02-10 00:41:49 +00:00
Chris Lattner
b06015aa69 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Jakob Stoklund Olesen
e8800b8d7c Identify predicate and optional-def operands when printing machine 
instructions.

llvm-svn: 93925
 2010-01-19 22:08:34 +00:00
Devang Patel
c0e17df3ce Replace DebugLocTuple with DILocation. 
llvm-svn: 93630
 2010-01-16 06:09:35 +00:00
Dale Johannesen
7b1a7ed330 Further progration of metadata operands. The 
dumper doesn't really do what I want yet, but
at least it doesn't crash now.

llvm-svn: 93272
 2010-01-13 00:00:24 +00:00
Jakob Stoklund Olesen
7725526de1 Add <imp-def> and <imp-kill> operands when replacing virtual sub-register defs and kills. 
An instruction like this:

  %reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0

Must be replaced with this when substituting physical registers:

  %S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>

llvm-svn: 92812
 2010-01-06 00:29:28 +00:00
David Greene
29388d6a6f Change errs() to dbgs(). 
llvm-svn: 92545
 2010-01-04 23:48:20 +00:00
Chris Lattner
5a409bd17a snip one more #include from Metadata.h 
llvm-svn: 92214
 2009-12-28 08:30:43 +00:00
Bill Wendling
ec030f2f01 Remove dead store. 
llvm-svn: 92159
 2009-12-25 13:45:50 +00:00
Bill Wendling
49fac47c83 Remove dead store from copy-pasto. 
llvm-svn: 92158
 2009-12-25 13:44:36 +00:00
Jim Grosbach
2a282f2f86 Add @earlyclobber TableGen constraint 
llvm-svn: 91554
 2009-12-16 19:43:02 +00:00
Evan Cheng
5c668a2259 Follow up to 90488. Turn a check into an assertion. 
llvm-svn: 90815
 2009-12-07 23:10:34 +00:00
Dan Gohman
33004b6302 Don't print the debug directory; it's often long and uninteresting. Omit 
the column number if it is not known. Handle the case of a missing filename
better.

llvm-svn: 90630
 2009-12-05 00:20:51 +00:00
Evan Cheng
8a19371370 Watch out for PHI instruction with no source operands. 
llvm-svn: 90488
 2009-12-03 21:50:58 +00:00
Evan Cheng
7145382389 Fill out codegen SSA updater. It's not yet tested. 
llvm-svn: 90395
 2009-12-03 02:31:43 +00:00
Dan Gohman
461b937053 Devang pointed out that this code should use DIScope instead of 
DICompileUnit. This code now prints debug filenames successfully.

llvm-svn: 90181
 2009-12-01 00:45:56 +00:00
Dan Gohman
2e3f187cbd Print the debug info line and column in MachineInstr::print even when there's 
no filename. This situation is apparently fairly common right now.

llvm-svn: 89701
 2009-11-23 21:29:08 +00:00
Dan Gohman
9b5eea30f7 Initialize the new AsmPrinterFlags field to 0, fixing uses of 
uninitialized memory.

llvm-svn: 88985
 2009-11-16 22:49:38 +00:00
Dan Gohman
2745d19287 Print "..." instead of all the uninteresting register clobbers on call 
instructions. This makes CodeGen dumps significantly less noisy.

Example before:
  BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>

Same example after:
  BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...

llvm-svn: 86583
 2009-11-09 19:38:45 +00:00
Dan Gohman
0080ee2d91 Use WriteAsOperand to print GlobalAddress MachineOperands. This 
prints them with the leading '@'.

llvm-svn: 86261
 2009-11-06 18:03:10 +00:00
Dan Gohman
34341e69c4 Make -print-machineinstrs more readable. 
- Be consistent when referring to MachineBasicBlocks: BB#0.
 - Be consistent when referring to virtual registers: %reg1024.
 - Be consistent when referring to unknown physical registers: %physreg10.
 - Be consistent when referring to known physical registers: %RAX
 - Be consistent when referring to register 0: %reg0
 - Be consistent when printing alignments: align=16
 - Print jump table contents.
 - Don't print host addresses, in general.
 - and various other cleanups.

llvm-svn: 85682
 2009-10-31 20:19:03 +00:00
Dan Gohman
6c9388011b Initial target-independent CodeGen support for BlockAddresses. 
llvm-svn: 85556
 2009-10-30 01:27:03 +00:00
Evan Cheng
f781bd8947 Need a comma after imp-use. 
llvm-svn: 84749
 2009-10-21 07:56:02 +00:00
Evan Cheng
70b1fa5a24 Print earlyclobber for implicit-defs as well. 
llvm-svn: 84152
 2009-10-14 23:37:31 +00:00
Devang Patel
d7ebfe3963 s/DebugLoc.CompileUnit/DebugLoc.Scope/g 
s/DebugLoc.InlinedLoc/DebugLoc.InlinedAtLoc/g

llvm-svn: 84054
 2009-10-13 23:28:53 +00:00
Dan Gohman
87b02d5bbc Factor out LiveIntervalAnalysis' code to determine whether an instruction 
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
 2009-10-09 23:27:56 +00:00
Dan Gohman
e19c1810d7 isTriviallyReMaterializable checks the 
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.

llvm-svn: 83671
 2009-10-09 21:02:10 +00:00