528560 Commits

Author SHA1 Message Date
Sterling-Augustine
864071dd7e
Bazel fixes for a778930f85b6d17cf31ff0e15964a7c7116e2a9d (#128783) 2025-02-25 14:56:38 -08:00
Paul Floyd
789bfdc3e6
[OMPT] Use __tsan_init to detect TSan binaries rather than RunningOnValgrind (#128357)
Switch to using __tsan_init rather than RunningOnValgrind as the means
for detecting TSan instumented binaries. RunningOnValgrind is present in
other libraries (such as Google perftools tcmalloc). An exe that links
with a tcmalloc static library and exports symbols with -rdynamic will
appear to be TSan instrumented even when it is not resulting in "Unable
to fint TSan function ..." messages.

Fixes issue #122319.
2025-02-25 23:35:32 +01:00
Valentin Clement (バレンタイン クレメン)
65cf534139
[flang][cuda] Add interfaces for __ldcg, __ldca, __ldcs, __ldlu, __ldcv, __stwb, __stcg, __stcs, __stwt (#128766) 2025-02-25 14:31:41 -08:00
Heejin Ahn
40566fd674
[WebAssembly] Generate invokes with llvm.wasm.(re)throw (#128105)
Even though `__builtin_wasm_throw`, which is lowered down to
`llvm.wasm.throw`, throws,
```cpp
try {
  __builtin_wasm_throw(0, obj);
} catch (...) {
}
```
does not generate `invoke`. This is because we have assumed the
intrinsic cannot be invoked, which doesn't make much sense. (See #128104
for the historical context)

#128104 made `llvm.wasm.throw` intrinsic invokable in the backend. This
actually generates `invoke`s in Clang for `__builtin_wasm_throw`.

While we're at it, this also generates `invoke`s for
`__builtin_wasm_rethrow`, which is actually not used anywhere in C++
support. I haven't deleted it just in case in may have uses later. (For
example, to support rethrow functionality that carries stack trace with
exnref)

Depends on #128104 for the CI to pass.
Fixes #124710.
2025-02-25 14:12:35 -08:00
Brox Chen
e6f6a1e863
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
Enable gisel selection for uaddsat and usubsat in true16 flow

This patch includes:

1. Added VGPR_16_Lo128/VGPR_16 to register bank and update register info
for recognizing 16bit regclass id and bit width
2. uaddsat/usubsat test update
2025-02-25 17:09:34 -05:00
Reid Kleckner
59cee030fb
Generalize creduce-clang-crash.py script to look for cvise (#128592)
cvise reimplements creduce in Python and bundles clang-delta and other
tools. In my experience, it is generally a more robust reduction tool
that is better maintained. I renamed the script to make it tool-neutral,
which also opens up the possibility that we teach it how to
automatically transition over to llvm-reduce and opt/llc to handle LLVM
backend crashes, but that is potential future work.

Internally, the variable names still say "creduce". I kept using the
verb "reduce" because "vise" is not a verb, but the external facing text
has been updated.
2025-02-25 13:59:26 -08:00
Michael Jones
8beec9fc48
[libc] implement a64l (#128758)
Implement the posix function a64l.
Standard:
https://pubs.opengroup.org/onlinepubs/9799919799/functions/a64l.html
2025-02-25 13:57:13 -08:00
Michael Jones
f4a80180f1
[libc] Move fileno and fdopen to fullbuild only (#128762)
Both fileno and fdopen require interfacing with the opaque FILE struct,
so they shouldn't be enabled in overlay mode. This patch moves both into
fullbuild only on all platforms.

Fixes #128643
2025-02-25 13:56:20 -08:00
Justin Bogner
44ffeecde2
[DXIL][Analysis] Make sure resource accessors are contiguous (#128696)
When some resource types were present, but not all of them, we were
ending up in a situation where we would fail to initialize the `FirstX`
variables and get incorrect iterators.

Fixes #128560.
2025-02-25 13:52:17 -08:00
David Olsen
ad94af973a
[CIR] React to breaking change to DataLayoutTypeInterface (#128772)
In #128754, `DataLayoutTypeInterface` was changed to give
`getPreferredAlignment` a default implemention. As a result, table-gen
no longer declared `getPreferredAlignment` when defining a class that
contained `[DeclareTypeInterfaceMethods<DataLayoutTypeInterface>]` in
the table-gen definition. That means all of the definitions in
`CIRTypes.cpp`, such as `PointerType::getPreferredAligment`, were
compilation errors.

Delete all the definitions of `getPreferredAlignment`. I verified that
the default implementation does the exact same thing as the explicit
overrides that are being deleted.
2025-02-25 13:44:24 -08:00
Christopher Bate
2646c36a86
[mlir][bufferization] Change OneShotModuleBufferize to not analyze or bufferize nested symbol tables (#127726)
The existing OneShotModuleBufferize will analyze and bufferize
operations which are in nested symbol tables (e.g. nested
`builtin.module`, `gpu.module`, or similar operations). This
behavior is untested and likely unintentional given other
limitations of OneShotModuleBufferize (`func.call` can't call
into nested symbol tables). This change reverses the existing
behavior so that the operations considered by the analysis and
bufferization exclude any operations in nested symbol table
scopes. Users who desire to bufferize nested modules can still do
so by applying the transformation in a pass pipeline or in a
custom pass. This further enables controlling the order in which
modules are bufferized as well as allowing use of different
options for different kinds of modules.
2025-02-25 14:23:11 -07:00
Farzon Lotfi
0be3f134c3
[DirectX] only allow intrinsics defined in DXIL.td (#128613)
Fixes #128071
The current behavior lets intrinsics that don't map to a DXILOP slip
through. Nothing catches this until we hit the DXIL validator. This
change fails earlier so we don't encode invalid llvm intrinsics that can
slip through because of clang builtins like `__builtin_reduce_and`
example:
https://hlsl.godbolt.org/z/13rPj18vn
2025-02-25 16:09:41 -05:00
Johannes de Fine Licht
303d7fa867
[MLIR][Interfaces] Make LoopLikeOpInterface inheritable outside of MLIR (#128743)
Many interface methods did not prefix the `mlir` namespace, which
prevented inheriting from this interface from an interface defined
outside the `mlir` namespace. Prefix namespaces everywhere to enable
this.
2025-02-25 15:54:25 -05:00
Justin Bogner
c79e867cd2
[DirectX] Update CBuffer to refer to a dx.Layout type (#128697)
This adds support cbuffers based on llvm/wg-hlsl#171 - the type argument
of the CBuffer TargetExtType is either a `dx.Layout` type which reports
its own size, or it's a normal type and we can simply refer to
DataLayout.
2025-02-25 12:36:29 -08:00
Jonas Hahnfeld
6a5dd04013 [Support] Try to fix AlignedCharArrayUnion with GCC 7.5
Work around "internal compiler error: Segmentation fault", apparently
caused by alignas(Ts...).
2025-02-25 21:35:01 +01:00
Thurston Dang
5e4938a991
Exclude hwasan from thread_create_failure.pass.cpp (#128768)
Fixes hwasan buildbot failure

(https://lab.llvm.org/buildbot/#/builders/55/builds/7536/steps/10/logs/stdio)
introduced in https://github.com/llvm/llvm-project/pull/125433 by
excluding this test for hwasan, similar to the existing exclusion of
asan.
2025-02-25 12:18:07 -08:00
Jonas Hahnfeld
f1025e671e
[Support] Replace deprecated std::aligned_union, NFCI. (#127417)
All std::aligned_* are deprecated in C++23. Implement the replacement
suggested in P1413R3 using alignas and std::max.
2025-02-25 21:00:14 +01:00
David Olsen
eacbcbe477
[CIR] Upstream type bool (#128601)
Support the type `bool` and the literals `true` and `false`. Add the
type `cir::BoolType` and the attribute `cir::BoolAttr` to ClangIR. Add
code in all the necessary places in ClangIR CodeGen to handle and to
recognize the type and the attribute.

Add test cases to existing tests func-simple.cpp and
global-var-simple.cpp.
2025-02-25 11:40:15 -08:00
Jeff Niu
4357a6603f
[mlir][DLTI] Make getPreferredAlignment default to getABIAlignment (#128754)
Many types don't have a preferred alignment, but often specifying an ABI
alignment is required to implement APIs on top of data layouts. Default
the preferred alignment to `getABIAlignment` to simplify things.
2025-02-25 11:32:36 -08:00
Philip Reames
00f02fed88
[RISCV] Change the vendor prefix for Rivos from "rv." to "ri." (#128761)
There had been concern raised about possible confusion with "rvv". After
internal discussion, we decided to go with an alternate prefix to reduce
possible confusion going forward. The specification document
(https://github.com/rivosinc/rivos-custom-extensions) has been updated.

And also add the XRivosVizip extension to the documentation. I'd missed
that in the initial commit.
2025-02-25 11:27:18 -08:00
Sam Elliott
f22291c791
[RISCV][NFC] Merge Xqci Decoder Tables (#128140)
RISC-V has multiple decoder tables because there is no guarantee that
non-standard extensions do not overlap with each other.

Qualcomm's Xqci family of extensions are intended to be implemented
together, and therefore we want a single decode table for this group of
extensions. This should be more efficient overall, and allows us to use
tablegen's existing mechanism that finds overlapping encodings within
the group.

To implement this, the key addition is `TRY_TO_DECODE_FEATURE_ANY`,
which will use the provided decoder table if any of the features from
the FeatureBitset (first argument) are enabled, rather than if all are
enabled.
2025-02-25 11:14:04 -08:00
Sam Elliott
c8136da26c
[RISCV] Correctly Decode Unsigned Immediates with Ranges (#128584)
We currently have two operands upstream that are an unsigned immediate
with a range constraint - `uimm8ge32` (for `cm.jalt`) and `uimm5gt3`
(for `qc.shladd`).

Both of these were using `decodeUImmOperand<N>` for decoding. For `Zcmt`
this worked, because the generated decoder automatically checked for
`cm.jt` first because the 8 undefined bits in `cm.jalt` are `000?????`
in `cm.jt` (this is to do with the range lower-bound being a
power-of-two). For Zcmt, this patch is NFC.

We have less luck with `Xqciac` - `qc.shladd` is being decoded where the
`uimm5` field is 3 or lower. This patch fixes this by introducing a
`decodeUImmOperandGE<Width, LowerBound>` helper, which will corretly
return `MCDisassembler::Fail` when the immediate is below the lower
bound.

I have added a test to show the encoding where `uimm5` is equal to 3 is
no longer disassembled as `qc.shladd`.
2025-02-25 11:12:08 -08:00
Brendan Dahl
9102afcd01
[WebAssembly] Use the same lowerings for f16x8 as other float vectors. (#127897)
This fixes failures to select the various compare operations that
weren't being expanded for f16x8.
2025-02-25 11:01:32 -08:00
LLVM GN Syncbot
7c266756ad [gn build] Port 66af4923ce24 2025-02-25 19:00:57 +00:00
Jonas Devlieghere
66af4923ce
[lldb-dap] Refactor reverse request response handlers (NFC) (#128594)
This refactors the response handlers for reverse request to follow the
same architecture as the request handlers. With only two implementation
that might be overkill, but it reduces code duplication and improves
error reporting by storing the sequence ID. This PR also fixes an
unchecked Expected in the old callback for unknown sequence IDs.
2025-02-25 13:00:26 -06:00
Alexey Samsonov
ab0e6fcaad
[libc][cmake] Clean up dead code in add_gen_header (#128753)
DATA_FILES CMake argument never existed in the new YAML-based hdrgen
version of add_gen_header function, and thus its uses added in
b1fd6f0996a9d6e6ebfa0cc3df0fe499c5ccdf65 were always dead code.

Remove them to clean up the function implementation.

Co-authored-by: Alexey Samsonov <samsonov@google.com>
2025-02-25 10:58:44 -08:00
Amir Ayupov
f567524399
[BOLT] Fix doTrace in BAT mode (#128546)
When processing BOLTed binaries with BAT section, we used to
indiscriminately use `BAT->getFallthroughsInTrace` to record
fall-throughs, even if the function is not covered by BAT.

Fix that by using non-BAT CFG-based `getFallthroughsInTrace` if the
function is not in BAT.

Test Plan: updated bolt-address-translation-yaml.test
2025-02-25 10:56:13 -08:00
Amir Ayupov
3968ebd00d
[BOLT] Keep multi-entry functions simple in aggregation mode (#128253)
BOLT used to mark multi-entry functions non-simple in non-relocation
mode with the reasoning that we can't move them due to potentially
undetected references. However, in aggregation mode it doesn't apply as
BOLT doesn't perform optimizations.

Relax this constraint in case of an aggregation job.

Test Plan: added entry-point-fallthru.s
2025-02-25 10:53:45 -08:00
Andrzej Warzyński
a778930f85
[mlir][linalg] Create a dedicated target for LinalgRelayoutInterface (#128485)
Creates an interface target for `LinalgRelayoutInterface`. This is
primarily to reduce the dependency of `Tensor` on `Linalg` to the
required minimum. For context and rationale, see:
  * https://github.com/llvm/llvm-project/issues/127668

Note, I also took the liberty of renaming `LinalgRelayoutInterface` as
`RelayoutOpInterface` (removed `Linalg`, added `Op`).
2025-02-25 18:48:08 +00:00
Brendan Dahl
67056c280a
[WebAssembly] Support shuffle for F16x8 vectors. (#127857) 2025-02-25 10:39:54 -08:00
Jon Chesterfield
43999deb37
[spirv][amdgpu] Set atomic size in the clang target info (#128569)
Problem identified by Joseph. The openmp device runtime uses
__scoped_atomic_load_n and similar which presently hit

```
error: large atomic operation may incur significant performance
      penalty; the access size (4 bytes) exceeds the max lock-free size (0 bytes) [-Werror,-Watomic-alignment]
```

This is because the spirv class doesn't set the corresponding field. The
base does, but only if there's a host toolchain, which there isn't.
2025-02-25 18:31:10 +00:00
Jerry-Ge
0a7809c644
[mlir][tosa] Fix ability to expand ranks with dynamic shape support (#128037)
- Fix ability to expand ranks with dynamic shape support
- Simplify the code

Signed-off-by: Suraj Sudhir <suraj.sudhir@arm.com>
Co-authored-by: Suraj Sudhir <suraj.sudhir@arm.com>
2025-02-25 10:21:50 -08:00
Craig Topper
4f18f3f09a
[RISCV] Use addiw for or_is_add when or input is sign extended. (#128635)
We prefer to emit addi instead of ori because its more compressible, but
this can pessimize the sext.w removal pass.

If the input to the OR is known to be a sign extended 32 bit value, we
can use addiw instead of addi which will give more power to the sext.w
removal pass. As it is known to produce sign a sign extended value and
only consume the lower 32 bits.

Fixes #128468.
2025-02-25 10:04:57 -08:00
Tai Ly
48db4e8377
[mlir][tosa] Change Transpose perms operand to attribute (#128115)
This patch changes the perms operand for Tosa Transpose operator to an
i32 array attribute

Signed-off-by: Tai Ly <tai.ly@arm.com>
2025-02-25 10:00:26 -08:00
Heejin Ahn
d2d469eb79
[WebAssembly] Make llvm.wasm.throw invokable (#128104)
`llvm.wasm.throw` intrinsic can throw but it was not invokable. Not sure
what the rationale was when it was first written that way, but I think
at least in Emscripten's C++ exception support with the Wasm port of
libunwind, `__builtin_wasm_throw`, which is lowered down to
`llvm.wasm.rethrow`, is used only within `_Unwind_RaiseException`, which
is an one-liner and thus does not need an `invoke`:
720e97f76d/system/lib/libunwind/src/Unwind-wasm.c (L69)
(`_Unwind_RaiseException` is called by `__cxa_throw`, which is generated
by the `throw` C++ keyword)

But this does not address other direct uses of the builtin in C++, whose
use I'm not sure about but is not prohibited. Also other language
frontends may need to use the builtin in different functions, which has
`try`-`catch`es or destructors.

This makes `llvm.wasm.throw` invokable in the backend. To do that, this
adds a custom lowering routine to `SelectionDAGBuilder::visitInvoke`,
like we did for `llvm.wasm.rethrow`.

This does not generate `invoke`s for `__builtin_wasm_throw` yet, which
will be done by a follow-up PR.

Addresses #124710.
2025-02-25 09:53:01 -08:00
Malavika Samak
041b7f5085
[Wunsafe-buffer-usage] Turn off unsafe-buffer warning for methods annotated with clang::unsafe_buffer_usage attribute (#125671)
Unsafe operation in methods that are already annotated with
clang::unsafe_buffer_usage attribute, should not trigger a warning. This
is because, the developer has already identified the method as unsafe
and warning at every unsafe operation is redundant.

rdar://138644831

---------

Co-authored-by: MalavikaSamak <malavika2@apple.com>
2025-02-25 23:09:26 +05:30
Mats Petersson
24b7759a9d
[FLANG][OpenMP]Add frontend support for ASSUME and ASSUMES (#120770)
Enough suport to parse correctly formed directives of !$OMP ASSUME and
!$OMP ASSUMES with teh related clauses that go with them: ABSENT,
CONTAINS, NO_OPENPP, NO_OPENMP_ROUTINES, NO_PARALLELISM and HOLDS.

Tests added for unparsing and dump parse-tree.

Semantics support is very minimal and no specific tests added.

The lowering will hit a TODO, and there are tests in Lower/OpenMP/Todo
to make it clear that this is currently expected behaviour.

---------

Co-authored-by: Kiran Chandramohan <kiran.chandramohan@arm.com>
Co-authored-by: Krzysztof Parzyszek <Krzysztof.Parzyszek@amd.com>
2025-02-25 17:36:25 +00:00
David Green
f08824b935 [AArch64] Add udiv and urem uniform tests. NFC
These should cost the same as non-uniform version.
2025-02-25 17:32:52 +00:00
Luke Hutton
53b46bb094
[mlir][tosa] Fix crash on attempt to fold int_div by zero (#128682)
Fixes #118268.

Signed-off-by: Luke Hutton <luke.hutton@arm.com>
2025-02-25 09:27:03 -08:00
Tai Ly
e58f475e84
[mlir][tosa] Move cond_if and while_loop operations to controlflow extension (#128216)
This commit adds the concept of a controlflow extension to the dialect
and updates the validation pass to check conf_if and while_loop are
supported only in the presence of the controlflow extension.

Signed-off-by: Luke Hutton <luke.hutton@arm.com>
Co-authored-by: Luke Hutton <luke.hutton@arm.com>
2025-02-25 09:26:02 -08:00
Marius Kamp
8bea511030
[X86] Fold AND(Y, XOR(X, SUB(0, X))) to ANDN(Y, BLSMSK(X)) (#128348)
XOR(X, SUB(0, X)) corresponds to a bitwise-negated BLSMSK instruction
(i.e., x ^ (x - 1)). On its own, this transformation is probably not
really profitable but when the XOR operation is an operand of an AND
operation, we can use an ANDN instruction to reduce the number of
emitted instructions by one.
    
Fixes #103501.
2025-02-25 17:11:00 +00:00
Kazu Hirata
9889de834b
[Utils] Avoid repeated hash lookups (NFC) (#128634) 2025-02-25 09:03:16 -08:00
Kazu Hirata
38f8ca1d18
[DebugInfo] Avoid repeated hash lookups (NFC) (#128632) 2025-02-25 09:02:52 -08:00
Nikolas Klauser
43401dd0b5
[libc++] Make .verify.cpp tests more robust against changing headers (#128703)
This is fixes the tests for the frozen headers, but is an improvement
either way.
2025-02-25 18:02:34 +01:00
Kazu Hirata
9388e42a3c
[CodeGen] Avoid repeated hash lookups (NFC) (#128631) 2025-02-25 09:02:19 -08:00
Kazu Hirata
791da3c5c2
[AsmPrinter] Avoid repeated hash lookups (NFC) (#128630) 2025-02-25 09:02:00 -08:00
Kazu Hirata
7501c9c0e1
[AsmParser] Avoid repeated map lookups (NFC) (#128629) 2025-02-25 09:01:34 -08:00
Julian Lettner
568106c215
[lldb][NFC] Fix comment in lldb/Core/ModuleList.h (#128602) 2025-02-25 08:52:03 -08:00
Kazu Hirata
99207ae835 [mlir] Fix a warning
This patch fixes:

  mlir/lib/Dialect/SPIRV/IR/ImageOps.cpp:33:24: error: unused variable
  'noSupportOperands' [-Werror,-Wunused-variable]
2025-02-25 08:51:33 -08:00
pkarveti
37559c8401
[Hexagon] Handle Call Operand vxi1 in Hexagon Backend (#128027)
This commit updates the Hexagon backend to handle
vxi1 call operands. It ensures compatibility for
vector types of sizes 4, 8, 16, 32, 64, and 128 x i1 when HVX is
enabled.

~Fixes #59009 and #118879~
2025-02-25 10:26:28 -06:00