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147 Commits

Author SHA1 Message Date
Craig Topper
a0869dceea Recommit r201059 and r201060 with hopefully a fix for its original failure. 
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.

llvm-svn: 201065
 2014-02-10 06:55:41 +00:00
Bob Wilson
ebdae7c2ff Revert r201059 and r201060. 
r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.

llvm-svn: 201064
 2014-02-10 05:28:30 +00:00
Craig Topper
0a43c2c393 Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. 
llvm-svn: 201060
 2014-02-10 01:58:12 +00:00
Craig Topper
0d88de8c56 Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. 
llvm-svn: 201059
 2014-02-10 00:50:34 +00:00
Craig Topper
fa6298a162 Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
llvm-svn: 200626
 2014-02-02 09:25:09 +00:00
Craig Topper
8e92e85ac7 Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix. 
llvm-svn: 200625
 2014-02-02 07:46:05 +00:00
Craig Topper
d402df3ce8 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
llvm-svn: 200624
 2014-02-02 07:08:01 +00:00
Craig Topper
10243c8907 Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
llvm-svn: 200522
 2014-01-31 08:47:06 +00:00
Craig Topper
ec68866f55 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
llvm-svn: 200520
 2014-01-31 07:00:55 +00:00
David Woodhouse
9bbf7ca13d ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) 
llvm-svn: 199806
 2014-01-22 15:08:36 +00:00
David Woodhouse
b33c2ef215 [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) 
llvm-svn: 199804
 2014-01-22 15:08:21 +00:00
David Woodhouse
2ef8d9c05c [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) 
llvm-svn: 199803
 2014-01-22 15:08:08 +00:00
David Woodhouse
caaa2850c0 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

llvm-svn: 199654
 2014-01-20 12:02:53 +00:00
Craig Topper
35da3d190a Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
llvm-svn: 199364
 2014-01-16 07:36:58 +00:00
Craig Topper
b7c7f38918 Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
llvm-svn: 199295
 2014-01-15 05:02:02 +00:00
Craig Topper
ad60708a72 Remove stray comma in enum to satisfy -Wpedantic. 
llvm-svn: 199194
 2014-01-14 08:07:10 +00:00
Craig Topper
ae11aed9d7 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
 2014-01-14 07:41:20 +00:00
David Woodhouse
32da3c8f3b [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759
 2014-01-08 12:58:24 +00:00
Craig Topper
2ea87dad77 The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
llvm-svn: 198589
 2014-01-06 06:57:27 +00:00
Craig Topper
d9e1669d1c Use patterns to remove some duplicate instructions. 
llvm-svn: 198550
 2014-01-05 06:55:48 +00:00
Craig Topper
34db6523f3 Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
llvm-svn: 198547
 2014-01-05 05:46:38 +00:00
Craig Topper
c0107977d9 Remove no longer needed x86 disassembler hack. 
llvm-svn: 198546
 2014-01-05 05:10:07 +00:00
Craig Topper
0550ce7ac1 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
llvm-svn: 198545
 2014-01-05 04:55:55 +00:00
Craig Topper
5165cf78b0 Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
llvm-svn: 198544
 2014-01-05 04:32:42 +00:00
Craig Topper
3484fc2161 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Craig Topper
5999d47538 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
llvm-svn: 198530
 2014-01-05 01:35:51 +00:00
Craig Topper
bc281ad8c1 Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
llvm-svn: 198515
 2014-01-04 22:29:41 +00:00
Craig Topper
1da8582322 Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
llvm-svn: 198475
 2014-01-04 05:09:27 +00:00
Craig Topper
66c20f344e Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
llvm-svn: 198336
 2014-01-02 19:12:10 +00:00
Craig Topper
fae226c67e Remove unused HasFROperands field from disassembler. 
llvm-svn: 198332
 2014-01-02 18:44:21 +00:00
Craig Topper
eabdbcb8a9 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
llvm-svn: 198327
 2014-01-02 18:20:48 +00:00
Craig Topper
a941d2b08e Remove unnecessary stirng comparison from disassembler. 
llvm-svn: 198325
 2014-01-02 17:41:40 +00:00
Craig Topper
9dd48c8ed4 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Craig Topper
83b7e24b76 Remove unused function argument. 
llvm-svn: 198291
 2014-01-02 03:58:45 +00:00
Craig Topper
3321c99a06 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
llvm-svn: 198284
 2014-01-01 21:52:57 +00:00
Craig Topper
9155118602 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
llvm-svn: 198278
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Craig Topper
623b0d64b3 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198276
 2014-01-01 14:22:37 +00:00
Craig Topper
e98c8cb9f0 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
llvm-svn: 198265
 2013-12-31 17:21:44 +00:00
Craig Topper
0e21bca6dd Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198238
 2013-12-30 19:16:48 +00:00
Craig Topper
6d776e2660 Remove EscapeFilter. It's funcionality can be covered by correctly using ExtendedFilter and ExactFilter. No functional change. 
llvm-svn: 198226
 2013-12-30 17:37:10 +00:00
Eric Christopher
c0a5aaeab0 [x86] Rename In32BitMode predicate to Not64BitMode 
That's what it actually means, and with 16-bit support it's going to be
a little more relevant since in a few corner cases we may actually want
to distinguish between 16-bit and 32-bit mode (for example the bare 'push'
aliases to pushw/pushl etc.)

Patch by David Woodhouse

llvm-svn: 197768
 2013-12-20 02:04:49 +00:00
Elena Demikhovsky
47fc44e52e AVX-512: Added legal type MVT::i1 and VK1 register for it. 
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.

llvm-svn: 197384
 2013-12-16 13:52:35 +00:00
Elena Demikhovsky
dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Craig Topper
a422b09ae3 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
llvm-svn: 192567
 2013-10-14 04:55:01 +00:00
Craig Topper
88adf2a49c Remove more filters from the disassembler. Mark some AVX512 instructions as CodeGenOnly. 
llvm-svn: 192525
 2013-10-12 05:41:08 +00:00
Craig Topper
aab53e7785 Mark some more instructions as CodeGenOnly. Remove filters from the disassembler. 
llvm-svn: 192522
 2013-10-12 04:46:18 +00:00
Craig Topper
81034928c6 Remove another unnecessary filter from the disassembler. 
llvm-svn: 192425
 2013-10-11 06:59:57 +00:00
Craig Topper
e1ceeb40c1 Fix so CRC32r64r8 isn't accidentally filtered from the disassembler tables. 
llvm-svn: 192339
 2013-10-10 04:26:52 +00:00
Craig Topper
2d0d180ab4 More x86 disassembler filtering cleanup. 
llvm-svn: 192279
 2013-10-09 06:12:53 +00:00