109 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
66d9572ced Position Independent Code (PIC) support [3]
llvm-svn: 42780
2007-10-09 03:15:11 +00:00
Duncan Sands
86e0119822 Fold the adjust_trampoline intrinsic into
init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841
2007-09-11 14:10:23 +00:00
Bruno Cardoso Lopes
14033fb5cb Changed stack allocation On LowerFORMAL_ARGUMENTS.
Added comments about new stack allocation.
Expand SelectCC for i32 results

llvm-svn: 41527
2007-08-28 05:08:16 +00:00
Bruno Cardoso Lopes
b10580ac1e InlineAsm asm support for integer registers added
llvm-svn: 41225
2007-08-21 16:09:25 +00:00
Bruno Cardoso Lopes
4bd7f4db9f Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddress
fixed to generate instructions (add, lui) glued!

llvm-svn: 41158
2007-08-18 02:16:30 +00:00
Duncan Sands
644f917358 Support for trampolines, except for X86 codegen which is
still under discussion.

llvm-svn: 40549
2007-07-27 12:58:54 +00:00
Bruno Cardoso Lopes
4449e5dd7f Fixed AddLiveOut issues
FI's created the write way to represent Mips stack

llvm-svn: 39760
2007-07-11 23:16:16 +00:00
Lauro Ramos Venancio
09d73c0305 Assert when TLS is not implemented.
llvm-svn: 39737
2007-07-11 17:19:51 +00:00
Bruno Cardoso Lopes
35e43c49b0 Initial Mips support, here we go! =)
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
2007-06-06 07:42:06 +00:00