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Commit Graph

115 Commits

Author SHA1 Message Date
Evan Cheng
be48a47d9d Remove the DoubleTy special case. 
llvm-svn: 33449
 2007-01-22 23:13:55 +00:00
Reid Spencer
a8a0f2cf68 Compensate for loss of DerivedTypes.h in TargetLowering.h 
llvm-svn: 33159
 2007-01-12 23:31:12 +00:00
Evan Cheng
376c9c4c97 CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg. 
llvm-svn: 32929
 2007-01-05 20:59:06 +00:00
Bill Wendling
22e978a736 Removing even more <iostream> includes. 
llvm-svn: 32320
 2006-12-07 20:04:42 +00:00
Evan Cheng
67fc141db5 Match TargetInstrInfo changes. 
llvm-svn: 32098
 2006-12-01 21:52:58 +00:00
Evan Cheng
20350c4025 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Evan Cheng
dbd3d294e6 Matches MachineInstr changes. 
llvm-svn: 31712
 2006-11-13 23:36:35 +00:00
Evan Cheng
979bbf48d5 Add methods to add implicit def use operands to a MI. 
llvm-svn: 31675
 2006-11-11 10:20:02 +00:00
Evan Cheng
8c9c6d71ed Add implicit def / use operands to MachineInstr. 
llvm-svn: 31633
 2006-11-10 08:43:01 +00:00
Evan Cheng
fd2c5dd806 Changes to use operand constraints to process two-address instructions. 
llvm-svn: 31453
 2006-11-04 09:44:31 +00:00
Chris Lattner
1fd360e13a handle global address constant sdnodes 
llvm-svn: 31323
 2006-10-31 20:01:56 +00:00
Evan Cheng
47fbeda5ce Debug tweak. 
llvm-svn: 30959
 2006-10-14 08:34:06 +00:00
Evan Cheng
45fe3bc72c Added support for machine specific constantpool values. These are useful for 
representing expressions that can only be resolved at link time, etc.

llvm-svn: 30278
 2006-09-12 21:00:35 +00:00
Chris Lattner
af23f9b5f6 Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Chris Lattner
d86418ab20 switch the SUnit pred/succ sets from being std::sets to being smallvectors. 
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%).  More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.

llvm-svn: 29743
 2006-08-17 00:09:56 +00:00
Evan Cheng
1640ae5a84 Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed. 
llvm-svn: 29545
 2006-08-07 22:12:12 +00:00
Jim Laskey
4e153f1b91 Use an enumeration to eliminate data relocations. 
llvm-svn: 29249
 2006-07-21 20:57:35 +00:00
Jim Laskey
f7300b2706 It was pointed out that DEBUG() is only available with -debug. 
llvm-svn: 29106
 2006-07-11 18:25:13 +00:00
Jim Laskey
c3d341ea98 Ensure that dump calls that are associated with asserts are removed from 
non-debug build.

llvm-svn: 29105
 2006-07-11 17:58:07 +00:00
Evan Cheng
55772ccfd6 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng
0c0996a97b commuteInstruction() does not always create a new MI! 
llvm-svn: 28592
 2006-05-31 18:03:39 +00:00
Evan Cheng
9d91caa053 Eliminate a memory leak. 
llvm-svn: 28585
 2006-05-31 07:13:03 +00:00
Evan Cheng
d8e2f6ebc1 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Chris Lattner
957cb6733a Move function-live-in-handling code from the sdisel code to the scheduler. 
This code should be emitted after legalize, so it can't be in sdisel.

Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG.  The X86 backend is the only one currently using this hook.

llvm-svn: 28315
 2006-05-16 06:10:58 +00:00
Evan Cheng
99f2f79e2f Fixing 2006-05-01-SchedCausingSpills.ll; some clean up 
llvm-svn: 28279
 2006-05-13 08:22:24 +00:00
Owen Anderson
8c2c1e90c4 Refactor a bunch of includes so that TargetMachine.h doesn't have to include 
TargetData.h.  This should make recompiles a bit faster with my current
TargetData tinkering.

llvm-svn: 28238
 2006-05-12 06:33:49 +00:00
Evan Cheng
095c9d9b7f Duh. That could take a long time. 
llvm-svn: 28235
 2006-05-12 06:05:18 +00:00
Evan Cheng
afed73eebe Add capability to scheduler to commute nodes for profit. 
If a two-address code whose first operand has uses below, it should be commuted
when possible.

llvm-svn: 28230
 2006-05-12 01:58:24 +00:00
Evan Cheng
d38c22bdd3 Refactor scheduler code. Move register-reduction list scheduler to a 
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.

llvm-svn: 28226
 2006-05-11 23:55:42 +00:00
Chris Lattner
469647bf38 Remove and simplify some more machineinstr/machineoperand stuff. 
llvm-svn: 28105
 2006-05-04 18:16:01 +00:00
Chris Lattner
10b71c0d08 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
llvm-svn: 28104
 2006-05-04 18:05:43 +00:00
Chris Lattner
940cc978ef Remove a bunch more SparcV9 specific stuff 
llvm-svn: 28093
 2006-05-04 01:15:02 +00:00
Owen Anderson
20a631fde7 Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. 
This fixes PR 759.

llvm-svn: 28074
 2006-05-03 01:29:57 +00:00
Nate Begeman
4ca2ea5b43 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
87b1dddb1c fix spello 
llvm-svn: 27053
 2006-03-24 07:15:07 +00:00
Chris Lattner
6b20104410 TargetData doesn't know the alignment of vectors :( 
llvm-svn: 26884
 2006-03-20 01:51:46 +00:00
Chris Lattner
a5b93b8c6d Move some simple-sched-specific instance vars to the simple scheduler. 
llvm-svn: 26690
 2006-03-10 07:42:02 +00:00
Chris Lattner
e015178de1 prune #includes 
llvm-svn: 26689
 2006-03-10 07:37:35 +00:00
Chris Lattner
4b70ff7876 move some simple scheduler methods into the simple scheduler 
llvm-svn: 26688
 2006-03-10 07:35:21 +00:00
Chris Lattner
dc2f135f5c Make EmitNode take a SDNode instead of a NodeInfo* 
llvm-svn: 26687
 2006-03-10 07:28:36 +00:00
Chris Lattner
b9d8fa0342 Move the VRBase field from NodeInfo to being a separate, explicit, map. 
llvm-svn: 26686
 2006-03-10 07:25:12 +00:00
Chris Lattner
2f8c7c3d55 Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy 
llvm-svn: 26682
 2006-03-10 06:34:51 +00:00
Chris Lattner
543832d39d Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner
2d945ba4c7 When a hazard recognizer needs noops to be inserted, do so. This represents 
noops as null pointers in the instruction sequence.

llvm-svn: 26564
 2006-03-05 23:51:47 +00:00
Evan Cheng
ed169db8a5 Added an offset field to ConstantPoolSDNode. 
llvm-svn: 26371
 2006-02-25 09:54:52 +00:00
Chris Lattner
5af3fdec12 Pass all the flags to the asm printer, not just the # operands. 
llvm-svn: 26362
 2006-02-24 19:50:58 +00:00
Chris Lattner
2f8a794b13 rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope. 
Add support for addressing modes.

llvm-svn: 26361
 2006-02-24 19:18:20 +00:00
Chris Lattner
86c51000db Refactor operand adding out to a new AddOperand method 
llvm-svn: 26358
 2006-02-24 18:54:03 +00:00
Chris Lattner
571d9647c6 Record all of the expanded registers in the DAG and machine instr, fixing 
several bugs in inline asm expanded operands.

llvm-svn: 26332
 2006-02-23 19:21:04 +00:00
Chris Lattner
4576bb74d5 Make MachineConstantPool entries alignments explicit 
llvm-svn: 26071
 2006-02-09 02:23:13 +00:00