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805 Commits

Author SHA1 Message Date
Chris Lattner
af3aefa10e Handle the trivial (but common) two-op case more efficiently 
llvm-svn: 24259
 2005-11-09 18:48:57 +00:00
Chris Lattner
c4d6050db6 Allocate the right amount of memory for this vector up front. 
llvm-svn: 24252
 2005-11-08 23:32:44 +00:00
Nate Begeman
d8f2a1a0f3 Allow custom lowered FP_TO_SINT ops in the check for whether a larger 
FP_TO_SINT is preferred to a larger FP_TO_UINT.  This seems to be begging
for a TLI.isOperationCustom() helper function.

llvm-svn: 23992
 2005-10-25 23:47:25 +00:00
Nate Begeman
5172ce641e Teach Legalize how to do something with EXTRACT_ELEMENT when the type of 
the pair of elements is a legal type.

llvm-svn: 23804
 2005-10-19 00:06:56 +00:00
Nate Begeman
bd5f41a6a6 Legalize BUILD_PAIR appropriately for upcoming 64 bit PowerPC work. 
llvm-svn: 23776
 2005-10-18 00:27:41 +00:00
Chris Lattner
b986f471be Use getExtLoad here instead of getNode, as extloads produce two values. This 
fixes a legalize failure on SPASS for itanium.

llvm-svn: 23747
 2005-10-15 20:24:07 +00:00
Nate Begeman
d59e5a7abb Relax the checking on zextload generation a bit, since as sabre pointed out 
you could be AND'ing with the result of a shift that shifts out all the
bits you care about, in addition to a constant.

Also, move over an add/sub_parts fold from legalize to the dag combiner,
where it works for things other than constants.  Woot!

llvm-svn: 23720
 2005-10-14 01:12:21 +00:00
Chris Lattner
258521d7ea When ExpandOp'ing a [SZ]EXTLOAD, make sure to remember that the chain 
is also legal.  Add support for ExpandOp'ing raw EXTLOADs too.

llvm-svn: 23716
 2005-10-13 21:44:47 +00:00
Chris Lattner
d23f4b7411 Implement PromoteOp for *EXTLOAD, allowing MallocBench/gs to Legalize 
llvm-svn: 23715
 2005-10-13 20:07:41 +00:00
Nate Begeman
c3a89c5259 Add support to Legalize for expanding i64 sextload/zextload into hi and lo 
parts. This should fix the crafty and signed long long unit test failure
on x86 last night.

llvm-svn: 23711
 2005-10-13 17:15:37 +00:00
Nate Begeman
02b23c6065 Move some Legalize functionality over to the DAGCombiner where it belongs. 
Kill some dead code.

llvm-svn: 23706
 2005-10-13 03:11:28 +00:00
Chris Lattner
7bf8d06f02 silence a bogus GCC warning 
llvm-svn: 23646
 2005-10-06 17:39:10 +00:00
Chris Lattner
4bbbb9eed7 Make the legalizer completely non-recursive 
llvm-svn: 23642
 2005-10-06 01:20:27 +00:00
Nate Begeman
f8221c5e2c Remove some bad code from Legalize 
llvm-svn: 23640
 2005-10-05 21:44:10 +00:00
Nate Begeman
5da6908d65 Fix some faulty logic in the libcall inserter. 
Since calls return more than one value, don't bail if one of their uses
happens to be a node that's not an MVT::Other when following the chain
from CALLSEQ_START to CALLSEQ_END.

Once we've found a CALLSEQ_START, we can just return; there's no need to
tail-recurse further up the graph.

Most importantly, just because something only has one use doesn't mean we
should use it's one use to follow from start to end.  This faulty logic
caused us to follow a chain of one-use FP operations back to a much earlier
call, putting a cycle in the graph from a later start to an earlier end.

This is a better fix that reverting to the workaround committed earlier
today.

llvm-svn: 23620
 2005-10-04 02:10:55 +00:00
Nate Begeman
54fb5002e5 Add back a workaround that fixes some breakages from chris's last change. 
Neither of us have yet figured out why this code is necessary, but stuff
breaks if its not there.  Still tracking this down...

llvm-svn: 23617
 2005-10-04 00:37:37 +00:00
Chris Lattner
9cfccfb517 Fix a problem where the legalizer would run out of stack space on extremely 
large basic blocks because it was purely recursive.  This switches it to an
iterative/recursive hybrid.

llvm-svn: 23596
 2005-10-02 17:49:46 +00:00
Chris Lattner
5b2be1f890 Fix two bugs in my patch earlier today that broke int->fp conversion on X86. 
llvm-svn: 23522
 2005-09-29 06:44:39 +00:00
Chris Lattner
6f3b577ee6 Add FP versions of the binary operators, keeping the int and fp worlds seperate. 
Though I have done extensive testing, it is possible that this will break
things in configs I can't test.  Please let me know if this causes a problem
and I'll fix it ASAP.

llvm-svn: 23504
 2005-09-28 22:28:18 +00:00
Chris Lattner
2d454bf5be Allow targets to say they don't support truncstore i1 (which includes a mask 
when storing to an 8-bit memory location), as most don't.

llvm-svn: 23303
 2005-09-10 00:20:18 +00:00
Chris Lattner
1a570f1fe4 Clean up some code from the last checkin 
llvm-svn: 23229
 2005-09-02 20:32:45 +00:00
Chris Lattner
630226697f Fix a bug in legalize where it would emit two calls to libcalls that return 
i64 values on targets that need that expanded to 32-bit registers.  This fixes
PowerPC/2005-09-02-LegalizeDuplicatesCalls.ll and speeds up 189.lucas from
taking 122.72s to 81.96s on my desktop.

llvm-svn: 23228
 2005-09-02 20:26:58 +00:00
Chris Lattner
d9af1aab51 Make sure to legalize assert[zs]ext's operand correctly 
llvm-svn: 23208
 2005-09-02 01:15:01 +00:00
Chris Lattner
7753f175e6 legalize ANY_EXTEND appropriately 
llvm-svn: 23204
 2005-09-02 00:18:10 +00:00
Chris Lattner
8a1a5f2818 Allow targets to custom expand shifts that are too large for their registers 
llvm-svn: 23173
 2005-08-31 19:01:53 +00:00
Chris Lattner
61d21b1f3c Fix FreeBench/fourinarow with the dag isel, by not adding a bogus result 
to SHIFT_PARTS nodes

llvm-svn: 23151
 2005-08-30 17:21:17 +00:00
Chris Lattner
9a4ad487f0 Fix a miscompile of PtrDist/bc. Sign extending bools is not the right thing, 
at least tends to expose problems elsewhere.

llvm-svn: 23149
 2005-08-30 16:56:19 +00:00
Nate Begeman
43144a2fe0 Add support for AssertSext and AssertZext, folding other extensions with 
them.  This allows for elminination of redundant extends in the entry
blocks of functions on PowerPC.

Add support for i32 x i32 -> i64 multiplies, by recognizing when the inputs
to ISD::MUL in ExpandOp are actually just extended i32 values and not real
i64 values.  this allows us to codegen

int mulhs(int a, int b) { return ((long long)a * b) >> 32; }
as:
_mulhs:
        mulhw r3, r4, r3
        blr

instead of:
_mulhs:
        mulhwu r2, r4, r3
        srawi r5, r3, 31
        mullw r5, r4, r5
        add r2, r2, r5
        srawi r4, r4, 31
        mullw r3, r4, r3
        add r3, r2, r3
        blr

with a similar improvement on x86.

llvm-svn: 23147
 2005-08-30 02:44:00 +00:00
Andrew Lenharth
835cbb364d Some of us cared about the the promote path 
llvm-svn: 23130
 2005-08-29 20:46:51 +00:00
Chris Lattner
dcde1b2b6a Fix an infinite loop on x86 
llvm-svn: 23129
 2005-08-29 17:30:00 +00:00
Chris Lattner
56ca46ee04 Nate noticed that Andrew never did this. This fixes PR600 
llvm-svn: 23110
 2005-08-26 22:50:40 +00:00
Chris Lattner
c30405e0ee Change ConstantPoolSDNode to actually hold the Constant itself instead of 
putting it into the constant pool.  This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.

llvm-svn: 23081
 2005-08-26 17:15:30 +00:00
Chris Lattner
c6d481db7a the 5th operand is the 4th number 
llvm-svn: 23074
 2005-08-26 00:43:46 +00:00
Chris Lattner
5f573416cd Add support for targets that want to custom expand select_cc in some cases. 
llvm-svn: 23071
 2005-08-26 00:23:59 +00:00
Chris Lattner
dff50cadaa Allow LowerOperation to return a null SDOperand in case it wants to lower 
some things given to it, but not all.

llvm-svn: 23070
 2005-08-26 00:14:16 +00:00
Chris Lattner
f12eb4d676 Start using isOperationLegal and isTypeLegal to simplify the code 
llvm-svn: 23012
 2005-08-24 16:35:28 +00:00
Nate Begeman
987121a61a Teach Legalize how to turn setcc into select_cc 
llvm-svn: 22977
 2005-08-23 04:29:48 +00:00
Chris Lattner
539c3fa863 When legalizing brcond ->brcc or select -> selectcc, make sure to truncate 
the old condition to a one bit value.  The incoming value must have been
promoted, and the top bits are undefined.  This causes us to generate:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r3, 17
        cmpwi cr0, r2, 0
        bne .LBB_test_2 ;
.LBB_test_1:    ;
        li r3, 1
.LBB_test_2:    ;
        blr

instead of:

_test:
        rlwinm r2, r3, 0, 31, 31
        li r2, 17
        cmpwi cr0, r3, 0
        bne .LBB_test_2 ;
.LBB_test_1:    ;
        li r2, 1
.LBB_test_2:    ;
        or r3, r2, r2
        blr

for:

int %test(bool %c) {
        %retval = select bool %c, int 17, int 1
        ret int %retval
}

llvm-svn: 22947
 2005-08-21 18:03:09 +00:00
Jim Laskey
b74c666186 Culling out use of unions for converting FP to bits and vice versa. 
llvm-svn: 22838
 2005-08-17 19:34:49 +00:00
Jim Laskey
686d6a1cb2 Switched to using BitsToDouble for int_to_float to avoid aliasing problem. 
llvm-svn: 22831
 2005-08-17 17:42:52 +00:00
Jim Laskey
898ba557d0 Change hex float constants for the sake of VC++. 
llvm-svn: 22828
 2005-08-17 09:44:59 +00:00
Jim Laskey
f2516a9180 Added generic code expansion for [signed|unsigned] i32 to [f32|f64] casts in the 
legalizer.  PowerPC now uses this expansion instead of ISel version.

Example:

// signed integer to double conversion
double f1(signed x) {
  return (double)x;
}

// unsigned integer to double conversion
double f2(unsigned x) {
  return (double)x;
}

// signed integer to float conversion
float f3(signed x) {
  return (float)x;
}

// unsigned integer to float conversion
float f4(unsigned x) {
  return (float)x;
}


Byte Code:

internal fastcc double %_Z2f1i(int %x) {
entry:
        %tmp.1 = cast int %x to double          ; <double> [#uses=1]
        ret double %tmp.1
}

internal fastcc double %_Z2f2j(uint %x) {
entry:
        %tmp.1 = cast uint %x to double         ; <double> [#uses=1]
        ret double %tmp.1
}

internal fastcc float %_Z2f3i(int %x) {
entry:
        %tmp.1 = cast int %x to float           ; <float> [#uses=1]
        ret float %tmp.1
}

internal fastcc float %_Z2f4j(uint %x) {
entry:
        %tmp.1 = cast uint %x to float          ; <float> [#uses=1]
        ret float %tmp.1
}

internal fastcc double %_Z2g1i(int %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.2 = cast int %x to uint            ; <uint> [#uses=1]
        %tmp.3 = xor uint %tmp.2, 2147483648            ; <uint> [#uses=1]
        %tmp.5 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %tmp.3, uint* %tmp.5
        %tmp.9 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.10 = load double* %tmp.9           ; <double> [#uses=1]
        %tmp.13 = load double* cast (long* %signed_bias to double*)             ; <double> [#uses=1]
        %tmp.14 = sub double %tmp.10, %tmp.13           ; <double> [#uses=1]
        ret double %tmp.14
}

internal fastcc double %_Z2g2j(uint %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.1 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %x, uint* %tmp.1
        %tmp.4 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.5 = load double* %tmp.4            ; <double> [#uses=1]
        %tmp.8 = load double* cast (long* %unsigned_bias to double*)            ; <double> [#uses=1]
        %tmp.9 = sub double %tmp.5, %tmp.8              ; <double> [#uses=1]
        ret double %tmp.9
}

internal fastcc float %_Z2g3i(int %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.2 = cast int %x to uint            ; <uint> [#uses=1]
        %tmp.3 = xor uint %tmp.2, 2147483648            ; <uint> [#uses=1]
        %tmp.5 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %tmp.3, uint* %tmp.5
        %tmp.9 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.10 = load double* %tmp.9           ; <double> [#uses=1]
        %tmp.13 = load double* cast (long* %signed_bias to double*)             ; <double> [#uses=1]
        %tmp.14 = sub double %tmp.10, %tmp.13           ; <double> [#uses=1]
        %tmp.16 = cast double %tmp.14 to float          ; <float> [#uses=1]
        ret float %tmp.16
}

internal fastcc float %_Z2g4j(uint %x) {
entry:
        %buffer = alloca [2 x uint]             ; <[2 x uint]*> [#uses=3]
        %tmp.0 = getelementptr [2 x uint]* %buffer, int 0, int 0                ; <uint*> [#uses=1]
        store uint 1127219200, uint* %tmp.0
        %tmp.1 = getelementptr [2 x uint]* %buffer, int 0, int 1                ; <uint*> [#uses=1]
        store uint %x, uint* %tmp.1
        %tmp.4 = cast [2 x uint]* %buffer to double*            ; <double*> [#uses=1]
        %tmp.5 = load double* %tmp.4            ; <double> [#uses=1]
        %tmp.8 = load double* cast (long* %unsigned_bias to double*)            ; <double> [#uses=1]
        %tmp.9 = sub double %tmp.5, %tmp.8              ; <double> [#uses=1]
        %tmp.11 = cast double %tmp.9 to float           ; <float> [#uses=1]
        ret float %tmp.11
}


PowerPC Code:

        .machine ppc970


        .const
        .align  2
.CPIl1__Z2f1i_0:                                        ; float 0x4330000080000000
        .long   1501560836      ; float 4.5036e+15
        .text
        .align  2
        .globl  l1__Z2f1i
l1__Z2f1i:
.LBBl1__Z2f1i_0:        ; entry
        xoris r2, r3, 32768
        stw r2, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl1__Z2f1i_0)
        lfs f1, lo16(.CPIl1__Z2f1i_0)(r2)
        fsub f1, f0, f1
        blr


        .const
        .align  2
.CPIl2__Z2f2j_0:                                        ; float 0x4330000000000000
        .long   1501560832      ; float 4.5036e+15
        .text
        .align  2
        .globl  l2__Z2f2j
l2__Z2f2j:
.LBBl2__Z2f2j_0:        ; entry
        stw r3, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl2__Z2f2j_0)
        lfs f1, lo16(.CPIl2__Z2f2j_0)(r2)
        fsub f1, f0, f1
        blr


        .const
        .align  2
.CPIl3__Z2f3i_0:                                        ; float 0x4330000080000000
        .long   1501560836      ; float 4.5036e+15
        .text
        .align  2
        .globl  l3__Z2f3i
l3__Z2f3i:
.LBBl3__Z2f3i_0:        ; entry
        xoris r2, r3, 32768
        stw r2, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl3__Z2f3i_0)
        lfs f1, lo16(.CPIl3__Z2f3i_0)(r2)
        fsub f0, f0, f1
        frsp f1, f0
        blr


        .const
        .align  2
.CPIl4__Z2f4j_0:                                        ; float 0x4330000000000000
        .long   1501560832      ; float 4.5036e+15
        .text
        .align  2
        .globl  l4__Z2f4j
l4__Z2f4j:
.LBBl4__Z2f4j_0:        ; entry
        stw r3, -4(r1)
        lis r2, 17200
        stw r2, -8(r1)
        lfd f0, -8(r1)
        lis r2, ha16(.CPIl4__Z2f4j_0)
        lfs f1, lo16(.CPIl4__Z2f4j_0)(r2)
        fsub f0, f0, f1
        frsp f1, f0
        blr

llvm-svn: 22814
 2005-08-17 00:39:29 +00:00
Chris Lattner
33182325f5 Eliminate the RegSDNode class, which 3 nodes (CopyFromReg/CopyToReg/ImplicitDef) 
used to tack a register number onto the node.

Instead of doing this, make a new node, RegisterSDNode, which is a leaf
containing a register number.  These three operations just become normal
DAG nodes now, instead of requiring special handling.

Note that with this change, it is no longer correct to make illegal
CopyFromReg/CopyToReg nodes.  The legalizer will not touch them, and this
is bad, so don't do it. :)

llvm-svn: 22806
 2005-08-16 21:55:35 +00:00
Nate Begeman
371e49515d Implement BR_CC and BRTWOWAY_CC. This allows the removal of a rather nasty 
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.

llvm-svn: 22805
 2005-08-16 19:49:35 +00:00
Chris Lattner
1973278b38 Add some methods for dag->dag isel. 
Split RemoveNodeFromCSEMaps out of DeleteNodesIfDead to do it.

llvm-svn: 22801
 2005-08-16 18:17:10 +00:00
Nate Begeman
d5e739dcc2 Fix last night's PPC32 regressions by 
1. Not selecting the false value of a select_cc in the false arm, which
   isn't legal for nested selects.
2. Actually returning the node we created and Legalized in the FP_TO_UINT
   Expander.

llvm-svn: 22789
 2005-08-14 18:38:32 +00:00
Nate Begeman
36853ee1fd Teach the legalizer how to legalize FP_TO_UINT. 
Teach the legalizer to promote FP_TO_UINT to FP_TO_SINT if the wider
  FP_TO_UINT is also illegal.  This allows us on PPC to codegen
  unsigned short foo(float a) { return a; }

as:
_foo:
.LBB_foo_0:     ; entry
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        rlwinm r3, r2, 0, 16, 31
        blr

instead of:
_foo:
.LBB_foo_0:     ; entry
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        lis r3, ha16(.CPI_foo_0)
        lfs f0, lo16(.CPI_foo_0)(r3)
        fcmpu cr0, f1, f0
        blt .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        fsubs f0, f1, f0
        fctiwz f0, f0
        stfd f0, -16(r1)
        lwz r2, -12(r1)
        xoris r2, r2, 32768
.LBB_foo_2:     ; entry
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 22785
 2005-08-14 01:20:53 +00:00
Nate Begeman
180b08897f Some SELECT_CC cleanups: 
1. move assertions for node creation to getNode()
2. legalize the values returned in ExpandOp immediately
3. Move select_cc optimizations from SELECT's getNode() to SELECT_CC's,
   allowing them to be cleaned up significantly.

This paves the way to pick up additional optimizations on SELECT_CC, such
as sum-of-absolute-differences.

llvm-svn: 22757
 2005-08-11 01:12:20 +00:00
Nate Begeman
e5b86d7442 Add new node, SELECT_CC. This node is for targets that don't natively 
implement SELECT.

llvm-svn: 22755
 2005-08-10 20:51:12 +00:00
Chris Lattner
d47675ed24 Eliminate the SetCCSDNode in favor of a CondCodeSDNode class. This pulls the 
CC out of the SetCC operation, making SETCC a standard ternary operation and
CC's a standard DAG leaf.  This will make it possible for other node to use
CC's as operands in the future...

llvm-svn: 22728
 2005-08-09 20:20:18 +00:00