Craig Topper
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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llvm-svn: 140954
2011-10-01 19:54:56 +00:00
Peter Collingbourne
84c287e33c
Move TableGen's parser and entry point into a library
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This is the first step towards splitting LLVM and Clang's tblgen executables.
llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Craig Topper
526adabe87
Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
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llvm-svn: 140370
2011-09-23 06:57:25 +00:00
Craig Topper
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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llvm-svn: 139484
2011-09-11 20:23:20 +00:00
Craig Topper
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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llvm-svn: 138997
2011-09-02 04:17:54 +00:00
Craig Topper
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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llvm-svn: 138552
2011-08-25 07:42:00 +00:00
Joerg Sonnenberger
fc4789da4a
Add support for the VIA PadLock instructions.
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llvm-svn: 128826
2011-04-04 16:58:13 +00:00
Joerg Sonnenberger
c94780c539
Use array_lengthof
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llvm-svn: 128823
2011-04-04 16:25:38 +00:00
Joerg Sonnenberger
fb3bce155e
Change loops to derive the number of tables automatically
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llvm-svn: 128818
2011-04-04 14:42:22 +00:00
Sean Callanan
c3fd523731
X86 table-generator and disassembler support for the AVX
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instruction set. This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures. Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.
llvm-svn: 127644
2011-03-15 01:23:15 +00:00
Benjamin Kramer
34402c4fe4
Constify another 2 disassembler tables.
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llvm-svn: 117208
2010-10-23 09:28:42 +00:00
Benjamin Kramer
de0a4fbf3b
Make the disassembler tables const so they end up in read-only memory.
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llvm-svn: 117206
2010-10-23 09:10:44 +00:00
Benjamin Kramer
9192e7ab12
Make some symbols static, move classes into anonymous namespaces.
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llvm-svn: 117111
2010-10-22 17:35:07 +00:00
Dan Gohman
b29cda9b3c
Fix a bunch of namespace polution.
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llvm-svn: 101376
2010-04-15 17:08:50 +00:00
Daniel Dunbar
c7dccd8ad2
Suppress compiler warning.
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llvm-svn: 91959
2009-12-23 00:45:10 +00:00
Nuno Lopes
91b866a163
fix build and while at it remove a redudant include
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llvm-svn: 91774
2009-12-19 11:52:18 +00:00
Daniel Dunbar
3a821f7f0c
More bzero -> memset that I missed.
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llvm-svn: 91757
2009-12-19 04:16:57 +00:00
Sean Callanan
04cc307edd
Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit
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incarnations), integrated into the MC framework.
The disassembler is table-driven, using a custom TableGen backend to
generate hierarchical tables optimized for fast decode. The disassembler
consumes MemoryObjects and produces arrays of MCInsts, adhering to the
abstract base class MCDisassembler (llvm/MC/MCDisassembler.h).
The disassembler is documented in detail in
- lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime)
- utils/TableGen/DisassemblerEmitter.cpp (table emitter)
You can test the disassembler by running llvm-mc -disassemble for i386
or x86_64 targets. Please let me know if you encounter any problems
with it.
llvm-svn: 91749
2009-12-19 02:59:52 +00:00
