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727 Commits

Author SHA1 Message Date
Chris Lattner
676c61db0e update a bunch of code to use the MachinePointerInfo version of getStore. 
llvm-svn: 114461
 2010-09-21 18:41:36 +00:00
Chris Lattner
6963c1f789 eliminate an old SelectionDAG::getTruncStore method, propagating 
MachinePointerInfo around more.

llvm-svn: 114452
 2010-09-21 17:42:31 +00:00
Chris Lattner
3d178ed4d4 propagate MachinePointerInfo through various uses of the old 
SelectionDAG::getExtLoad overload, and eliminate it.

llvm-svn: 114446
 2010-09-21 17:04:51 +00:00
Chris Lattner
f72c3c08a4 convert dagcombine off the old form of getLoad. This fixes several bugs 
with SVOffset computation.

llvm-svn: 114442
 2010-09-21 16:08:50 +00:00
Chris Lattner
e32675253f simplify DAGCombiner::SimplifySelectOps step #2/2. 
llvm-svn: 114437
 2010-09-21 15:58:55 +00:00
Chris Lattner
254c445e63 substantially reduce indentation and simplify DAGCombiner::SimplifySelectOps. 
no functionality change (step #1)

llvm-svn: 114436
 2010-09-21 15:46:59 +00:00
Chris Lattner
a35499e2af a few more trivial updates. This fixes PerformInsertVectorEltInMemory to not 
pass a completely incorrect SrcValue, which would result in a miscompile with
combiner-aa.

llvm-svn: 114411
 2010-09-21 07:32:19 +00:00
Owen Anderson
272ff94916 When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore, 
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.

llvm-svn: 114348
 2010-09-20 20:39:59 +00:00
Owen Anderson
7b8d2ae912 Revert r114312 while I sort out some issues. 
llvm-svn: 114313
 2010-09-19 21:01:26 +00:00
Owen Anderson
ff82f8a35b Tentatively enabled DAGCombiner Alias Analysis by default. As far as I know, 
r114268 fixed the last of the blockers to enabling it.  I will be monitoring
for failures.

llvm-svn: 114312
 2010-09-19 19:51:55 +00:00
Dan Gohman
3c9b5f394b Don't narrow the load and store in a load+twiddle+store sequence unless 
there are clearly no stores between the load and the store. This fixes
this miscompile reported as PR7833.

This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is
safe, but awkward to prove safe. Move it to X86's README.txt.

llvm-svn: 112861
 2010-09-02 21:18:42 +00:00
Nate Begeman
317b969ac5 Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself 
recursively and returning a SCALAR_TO_VECTOR node, but assuming the input was always a BUILD_VECTOR.

llvm-svn: 109519
 2010-07-27 18:02:18 +00:00
Owen Anderson
9c271e2835 Remove r108639 now that it is handled by InstCombine instead. 
llvm-svn: 108688
 2010-07-19 08:10:24 +00:00
Owen Anderson
f7f9c8a2f7 Add a DAGCombine xform to fold away redundant float->double->float conversions around sqrt instructions. 
I am assured by people more knowledgeable than me that there are no rounding issues in eliminating this.

This fixed <rdar://problem/8197504>.

llvm-svn: 108639
 2010-07-18 08:47:54 +00:00
Duncan Sands
41b4a6b36a Convert some tab stops into spaces. 
llvm-svn: 108130
 2010-07-12 08:16:59 +00:00
Bob Wilson
21eed476e8 Reenable DAG combining for vector shuffles. It looks like it was temporarily 
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941
 2010-07-09 00:38:12 +00:00
Benjamin Kramer
0ae3f08c0d Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms. 
llvm-svn: 107868
 2010-07-08 12:09:56 +00:00
Evan Cheng
1c349f18f8 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake. 
llvm-svn: 107820
 2010-07-07 22:15:37 +00:00
Devang Patel
a3ca21b228 Propagate debug loc. 
llvm-svn: 107710
 2010-07-06 22:08:15 +00:00
Bob Wilson
269a89fd3a Unlike other targets, ARM now uses BUILD_VECTORs post-legalization so they 
can't be changed arbitrarily by the DAGCombiner without checking if it is
running after legalization.

llvm-svn: 107097
 2010-06-28 23:40:25 +00:00
Duncan Sands
2dc70bea54 Remove variables which are assigned to but for which the value 
is not used.  Spotted by gcc-4.6.

llvm-svn: 106854
 2010-06-25 14:48:39 +00:00
Dan Gohman
600f62b3ba Reapply r106634, now that the bug it exposed is fixed. 
llvm-svn: 106746
 2010-06-24 14:30:44 +00:00
Daniel Dunbar
4df321b7ad Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled. 
llvm-svn: 106634
 2010-06-23 17:09:26 +00:00
Jim Grosbach
b58c08b0ba Some targets don't require the fencing MEMBARRIER instructions surrounding 
atomic intrinsics, either because the use locking instructions for the
atomics, or because they perform the locking directly. Add support in the
DAG combiner to fold away the fences.

llvm-svn: 106630
 2010-06-23 16:07:42 +00:00
Dan Gohman
b92156d5e4 Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass, 
which is faster, simpler, and less surprising.

llvm-svn: 106263
 2010-06-18 01:05:21 +00:00
Dale Johannesen
60fe2cdc4f Fix another variant of PR 7191. Also add a testcase 
Mon Ping provided; unfortunately bugpoint failed to
reduce it, but I think it's important to have a test for
this in the suite.  8023512.

llvm-svn: 104624
 2010-05-25 18:47:23 +00:00
Dale Johannesen
ff384ad981 Fix PR 7191. I have been unable to create a .ll file that fails, sorry. 
(oye, a word which should be better known to people writing tree
traversals, means grandchild.)

llvm-svn: 104619
 2010-05-25 17:50:03 +00:00
Bob Wilson
61438fe064 Clean up extra whitespace. 
llvm-svn: 104410
 2010-05-21 23:53:55 +00:00
Bob Wilson
51d9ee3ff6 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
 2010-05-21 21:05:32 +00:00
Bob Wilson
42603958fb Optimize away insertelement of an undef value. This shows up in 
test/Codegen/ARM/reg_sequence.ll but it doesn't affect the generated code
because the coalescer cleans it up.  Radar 7998853.

llvm-svn: 104185
 2010-05-19 23:42:58 +00:00
Evan Cheng
abd0ad54a4 Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. 
The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.

Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.

llvm-svn: 104094
 2010-05-19 01:08:17 +00:00
Evan Cheng
f19384d54a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 
llvm-svn: 104060
 2010-05-18 21:31:17 +00:00
Evan Cheng
48f0de96d6 FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)). 
llvm-svn: 104004
 2010-05-18 00:03:40 +00:00
Evan Cheng
02947a4551 Be careful with operand promotion. For a binary operation, the source operands may be the same. PR7018. rdar://7939869. 
llvm-svn: 103419
 2010-05-10 19:03:57 +00:00
Dan Gohman
e82c25e878 Apply a patch from Jan Sjodin to fix a compiler abort on vector 
comparisons sign-extended to a different bitwidth than the
comparison operands.

llvm-svn: 102721
 2010-04-30 17:19:19 +00:00
Evan Cheng
f100557c9a Try operation promotion only if regular dag combine and target-specific ones failed to do anything. 
llvm-svn: 102492
 2010-04-28 07:10:39 +00:00
Evan Cheng
e813690b7a - When legal, promote a load to zextload rather than ext load. 
- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)

llvm-svn: 102455
 2010-04-27 19:48:13 +00:00
Evan Cheng
0abb54d631 When a load operand is promoted to an extload, replace other uses with uses of extload result truncated. 
llvm-svn: 102236
 2010-04-24 04:43:44 +00:00
Dan Gohman
5544b0c588 Apply a fix for a vector setcc dagcombine from Jan Sjodin. No 
testcase yet, as the testcase now fails downstream.

llvm-svn: 102228
 2010-04-24 01:17:30 +00:00
Evan Cheng
b9ff130d47 Code refactoring. 
llvm-svn: 102202
 2010-04-23 19:10:30 +00:00
Evan Cheng
f1223bdec0 - It's not safe to promote rotates (at least not trivially). 
- Some code refactoring.

llvm-svn: 102111
 2010-04-22 20:19:46 +00:00
Bill Wendling
467e6c2deb The visitXOR method can return the same SDNode. If so, we don't want to delete 
it as it's not dead.

llvm-svn: 101855
 2010-04-20 01:25:01 +00:00
Evan Cheng
e19aa5cc52 More progress on promoting i16 operations to i32 for x86. Work in progress. 
llvm-svn: 101808
 2010-04-19 19:29:22 +00:00
Evan Cheng
f1bd5fcdb4 More work to allow dag combiner to promote 16-bit ops to 32-bit. 
llvm-svn: 101621
 2010-04-17 06:13:15 +00:00
Evan Cheng
f037f87bde (i32 sext_in_reg (i32 aext (i16 x)), i16) -> (i32 sext x). No known test case until -promote-16bit is enabled. 
llvm-svn: 101551
 2010-04-16 22:26:19 +00:00
Evan Cheng
af56facacd Adding support for dag combiner to promote operations for profit. This requires target specific queries. For example, x86 should promote i16 to i32 when it does not impact load folding. 
x86 support is off by default. It can be enabled with -promote-16bit.

Work in progress.

llvm-svn: 101448
 2010-04-16 06:14:10 +00:00
Chris Lattner
3245afdf05 enhance the load/store narrowing optimization to handle a 
tokenfactor in between the load/store.  This allows us to 
optimize test7 into:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	(%rdx), %eax
                                        ## kill: SIL<def> ESI<kill>
	movb	%sil, 5(%rdi)
	ret

instead of:

_test7:                                 ## @test7
## BB#0:                                ## %entry
	movl	4(%esp), %ecx
	movl	$-65281, %eax           ## imm = 0xFFFFFFFFFFFF00FF
	andl	4(%ecx), %eax
	movzbl	8(%esp), %edx
	shll	$8, %edx
	addl	%eax, %edx
	movl	12(%esp), %eax
	movl	(%eax), %eax
	movl	%edx, 4(%ecx)
	ret

llvm-svn: 101355
 2010-04-15 06:10:49 +00:00
Chris Lattner
6ebd8674eb teach codegen to turn trunc(zextload) into load when possible. 
This doesn't occur much at all, it only seems to formed in the case
when the trunc optimization kicks in due to phase ordering.  In that
case it is saves a few bytes on x86-32.

llvm-svn: 101350
 2010-04-15 05:40:59 +00:00
Chris Lattner
f9b2e3c68a add a simple dag combine to replace trivial shl+lshr with 
and.  This happens with the store->load narrowing stuff.

llvm-svn: 101348
 2010-04-15 05:28:43 +00:00
Chris Lattner
4041ab6e00 Implement rdar://7860110 (also in target/readme.txt) narrowing 
a load/or/and/store sequence into a narrower store when it is
safe.  Daniel tells me that clang will start producing this sort
of thing with bitfields, and this does  trigger a few dozen times
on 176.gcc produced by llvm-gcc even now.

This compiles code like CodeGen/X86/2009-05-28-DAGCombineCrash.ll 
into:

        movl    %eax, 36(%rdi)

instead of:

        movl    $4294967295, %eax       ## imm = 0xFFFFFFFF
        andq    32(%rdi), %rax
        shlq    $32, %rcx
        addq    %rax, %rcx
        movq    %rcx, 32(%rdi)

and each of the testcases into a single store.  Each of them used
to compile into craziness like this:

_test4:
	movl	$65535, %eax            ## imm = 0xFFFF
	andl	(%rdi), %eax
	shll	$16, %esi
	addl	%eax, %esi
	movl	%esi, (%rdi)
	ret

llvm-svn: 101343
 2010-04-15 04:48:01 +00:00