990 Commits

Author SHA1 Message Date
Saleem Abdulrasool
820e927d6f Basic: whitespace fixup for ARM target info
Fix whitespace.  NFC.

llvm-svn: 217955
2014-09-17 14:50:19 +00:00
James Molloy
0ffb093931 [ARM] Add ACLE predefines: maxmin, rounding and h/w integer division
Patch by Assad Hashmi!

llvm-svn: 217760
2014-09-15 11:25:38 +00:00
JF Bastien
b41724622b No need to use PNaCl's calling convention since PNaCl now uses a separate approach for calling conventions.
llvm-svn: 217696
2014-09-12 17:52:51 +00:00
JF Bastien
643817d929 Add support for le64.
Summary:
le64 is a generic little-endian 64-bit processor, mimicking le32.

Also see the associated LLVM change.

Test Plan: make check-all

Reviewers: dschuff

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5318

llvm-svn: 217694
2014-09-12 17:52:47 +00:00
Aaron Ballman
e9c6479c4d Fixing MSVC warning: "warning C4373: 'blah': virtual function overrides 'blah', previous versions of the compiler did not override when parameters only differed by const/volatile qualifiers."
This warning is basically useless because the "previous versions" being referred to is MSVC 2005 and earlier, and we obviously do not care about them. However, this warning isn't particularly chatty (I don't recall ever seeing it previously), and it has the opportunity to point out cases where the cv-qualifiers differ unintentionally (like this case), so I am leaving it enabled for now.

llvm-svn: 216267
2014-08-22 13:26:37 +00:00
Akira Hatanaka
987f1864ca [AArch64, inline-asm] Improve diagnostic that is printed when the size of a
variable that has regiser constraint "r" is not 64-bit.

General register operands are output using 64-bit "x" register names, regardless
of the size of the variable, unless the asm operand is prefixed with the "%w"
modifier. This surprises and confuses many users who aren't familiar with
aarch64 inline assembly rules.

With this commit, a note and fixit hint are printed which tell the users that
they need modifier "%w" in order to output a "w" register instead of an "x"
register.

<rdar://problem/12764785>

llvm-svn: 216260
2014-08-22 06:05:21 +00:00
Tom Stellard
a96344b50d R600: Implement getPointerWidthV()
This fixes a crash in the OCL_ImgProc/Canny OpenCV test.

NOTE: This is a candidate for the 3.5 branch.
llvm-svn: 216181
2014-08-21 13:58:40 +00:00
Tom Stellard
9affba4f9d R600: Add processor type for hainan
llvm-svn: 216180
2014-08-21 13:58:38 +00:00
Rafael Espindola
764837431a Delete support for AuroraUX.
auroraux.org is not resolving.

llvm-svn: 215644
2014-08-14 15:14:51 +00:00
Bob Wilson
a2acb1e84e Add predefined macros to identify x86_64h architectures.
Patch by Jim Grosbach.

llvm-svn: 215260
2014-08-08 23:46:28 +00:00
Bob Wilson
2a3710ec9e Change __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ for versions > 10.9.
The previous encoding only allowed a single digit for the minor version
number. This changes it to use 2 digits for both the minor version and the
revision number.

llvm-svn: 215245
2014-08-08 21:45:53 +00:00
Tim Northover
00853e5b6a MachO: set sizeof result type to what embedded headers expect.
Embedded systems seem to have inherited Darwin's choise of "unsigned long" for
size_t (via a bunch of headers), so we should respect that.

rdar://problem/17872787

llvm-svn: 214854
2014-08-05 11:07:26 +00:00
Pavel Chupin
fd223e1680 [x32] Add __int128 support
Summary:
Adding __int128 support explicitly for x86_64 because currently it's on
only when pointer size >= 64 which is not the case for x32.

Test Plan: One of the tests using __int128 is updated

Reviewers: atanasyan, chandlerc

Subscribers: cfe-commits, rob.khasanov, zinovy.nis, dschuff

Differential Revision: http://reviews.llvm.org/D4755

llvm-svn: 214710
2014-08-04 12:39:43 +00:00
Joerg Sonnenberger
254f8729d0 Let's assume PowerPC has no SSE.
llvm-svn: 214562
2014-08-01 21:20:02 +00:00
Robert Khasanov
3b6616c3a3 [SKX] Enabling SKX target (Skylake server chip)
a) add SKX support to Clang driver;
b) add tests for SKX target and AVX512BW, AVX512DQ, AVX512VL features into clang driver tests

Patch by Zinovy Nis <zinovy.y.nis@intel.com>

llvm-svn: 214306
2014-07-30 13:53:40 +00:00
Ulrich Weigand
8afad61a93 [PowerPC] Support ELFv1/ELFv2 ABI selection via -mabi= option
While Clang now supports both ELFv1 and ELFv2 ABIs, their use is currently
hard-coded via the target triple: powerpc64-linux is always ELFv1, while
powerpc64le-linux is always ELFv2.

These are of course the most common scenarios, but in principle it is
possible to support the ELFv2 ABI on big-endian or the ELFv1 ABI on
little-endian systems (and GCC does support that), and there are some
special use cases for that (e.g. certain Linux kernel versions could
only be built using ELFv1 on LE).

This patch implements the Clang side of supporting this, based on the
LLVM commit 214072.  The command line options -mabi=elfv1 or -mabi=elfv2
select the desired ABI if present.  (If not, Clang uses the same default
rules as now.)

Specifically, the patch implements the following changes based on the
presence of the -mabi= option:

In the driver:
- Pass the appropiate -target-abi flag to the back-end
- Select the correct dynamic loader version (/lib64/ld64.so.[12])

In the preprocessor:
- Define _CALL_ELF to the appropriate value (1 or 2)

In the compiler back-end:
- Select the correct ABI in TargetInfo.cpp
- Select the desired ABI for LLVM via feature (elfv1/elfv2)

llvm-svn: 214074
2014-07-28 13:17:52 +00:00
Tom Stellard
14e03967ab R600: Add processor type for Mullins
llvm-svn: 213999
2014-07-26 01:05:20 +00:00
James Molloy
8a157bf8f2 Revert part of r206963
Specifically the part where we removed a warning to be compatible with GCC, which has been widely regarded as a bad idea.

I'm not quite happy with how obtuse this warning is, especially in the fairly common case of a 32-bit integer literal, so I've got another patch awaiting review that adds a fixit to reduce confusion.

llvm-svn: 213935
2014-07-25 10:19:47 +00:00
Tim Northover
40956e64f2 AArch64: update Clang for merged arm64/aarch64 triples.
The main subtlety here is that the Darwin tools still need to be given "-arch
arm64" rather than "-arch aarch64". Fortunately this already goes via a custom
function to handle weird edge-cases in other architectures, and it tested.

I removed a few arm64_be tests because that really isn't an interesting thing
to worry about. No-one using big-endian is also referring to the target as
arm64 (at least as far as toolchains go). Mostly they date from when arm64 was
a separate target and we *did* need a parallel name simply to test it at all.
Now aarch64_be is sufficient.

llvm-svn: 213744
2014-07-23 12:32:58 +00:00
Akira Hatanaka
88ef728f2e [X86 inline-asm] Error out on inline-asm constraint "=f".
<rdar://problem/17476689>

llvm-svn: 213428
2014-07-18 23:30:30 +00:00
Kevin Qin
110db6f2ad [AArch64] Implement Clang CLI interface proposal about "-march".
1. Revert "Add default feature for CPUs on AArch64 target in Clang"
at r210625. Then, all enabled feature will by passed explicitly by
-target-feature in -cc1 option.

2. Get "-mfpu" deprecated.

3. Implement support of "-march". Usage is:
    -march=armv8-a+[no]feature
  For instance, "-march=armv8-a+neon+crc+nocrypto". Here "armv8-a" is
  necessary, and CPU names are not acceptable. Candidate features are
  fp, neon, crc and crypto. Where conflicting feature modifiers are
  specified, the right-most feature is used.

4. Implement support of "-mtune". Usage is:
    -march=CPU_NAME
  For instance, "-march=cortex-a57". This option will ONLY get
  micro-architectural feature enabled specifying to target CPU,
  like "+zcm" and "+zcz" for cyclone. Any architectural features
  WON'T be modified.

5. Change usage of "-mcpu" to "-mcpu=CPU_NAME+[no]feature", which is
  an alias to "-march={feature of CPU_NAME}+[no]feature" and
  "-mtune=CPU_NAME" together. Where this option is used in conjunction
  with -march or -mtune, those options take precedence over the
  appropriate part of this option.

llvm-svn: 213353
2014-07-18 07:03:22 +00:00
Saleem Abdulrasool
c68237bc2c Driver: bifurcate extended and basic MSC versioning
This restores the original behaviour of -fmsc-version. The older option
remains as a mechanism for specifying the basic version information. A
secondary option, -fms-compatibility-version permits the user to specify an
extended version to the driver.

The new version takes the value as a dot-separated value rather than the
major * 100 + minor format that -fmsc-version format. This makes it easier to
specify the value as well as a more flexible manner for specifying the value.

Specifying both values is considered an error.

The older parameter is left solely as a driver option, which is normalised into
the newer parameter. This allows us to retain a single code path in the
compiler itself whilst preserving the semantics of the old parameter as well as
avoid having to determine which of two formats are being used by the invocation.

The test changes are due to the fact that the compiler no longer supports the
old option, and is a direct conversion to the new option.

llvm-svn: 213119
2014-07-16 03:13:50 +00:00
Joerg Sonnenberger
9b7060e218 Drop separate UIntMaxType and just derive it from IntMaxType.
llvm-svn: 212987
2014-07-14 21:00:38 +00:00
Joerg Sonnenberger
3809a7a9f6 Introduce getCorrespondingUnsignedType() in TargetInfo to work like the
corresponding AST context function, only restricted to basic integer
types. Use this to ensure getUIntPtrType() gives types consistent with
getIntPtrType(). Fix NVPTX backend to give signed intptr_t.

llvm-svn: 212982
2014-07-14 20:40:56 +00:00
Alp Toker
958027b698 Fix typos
Also consolidate 'backward compatibility'

llvm-svn: 212974
2014-07-14 19:42:55 +00:00
David Blaikie
40f842de9c Remove use of uniform initialization ({}) introduced in r212725 since this isn't supported in MSVC.
llvm-svn: 212754
2014-07-10 18:46:15 +00:00
Zinovy Nis
1db9573f03 [x32] Adding X32 target support to driver, including TargetInfo,DescriptionString, flags, paths lookup, etc. Cover changes with new tests. The author of the patch is Pavel Chupin (@pavel.v.chupin).
The changes enable "hello world" on x32 target (x86_64-*-linux-gnux32). s/isX32/IsX32/ also fixed.

Differential Revision: http://reviews.llvm.org/D4180

llvm-svn: 212725
2014-07-10 15:27:19 +00:00
Daniel Sanders
9500d2d751 [mips][mips64r6] Define _MIPS_FPSET, __mips_fpr, and __mips_nan2008 correctly on MIPS32r6/MIPS64r6
Summary:
This removes the need to pass -mnan=2008 explicitly to be able to compile
the test-suite for MIPS32r6/MIPS64r6.

Differential Revision: http://reviews.llvm.org/D4433

llvm-svn: 212619
2014-07-09 13:56:23 +00:00
Daniel Sanders
cfbb71dfb6 [mips] clz is defined to give 32 for zero. Similarly, dclz gives 64.
Summary:
While debugging another issue, I noticed that Mips currently specifies that the
count leading zero builtins are undefined when the input is zero. The
architecture specifications say that the clz and dclz instructions write 32 or
64 respectively when given zero.

This doesn't fix any bugs that I'm aware of but it may improve optimisation in
some cases.

Differential Revision: http://reviews.llvm.org/D4431

llvm-svn: 212618
2014-07-09 13:43:19 +00:00
Tim Northover
e8c3721165 ARM: use LLVM's atomicrmw instructions when ldrex/strex are available.
Having some kind of weird kernel-assisted ABI for these when the
native instructions are available appears to be (and should be) the
exception; OSs have been gradually opting in for years and the code
was getting silly.

So let LLVM decide whether it's possible/profitable to inline them by
default.

Patch by Phoebe Buckheister.

llvm-svn: 212598
2014-07-09 09:24:43 +00:00
Alp Toker
80758084f7 Use non-intrusive refcounting for TargetOptions
llvm-svn: 212388
2014-07-06 05:26:44 +00:00
Simon Atanasyan
4e16a4250d [Driver][Mips] Support one more MIPS CPU name - octeon.
llvm-svn: 212339
2014-07-04 12:37:04 +00:00
Simon Atanasyan
26610c5960 [Driver][Mips] Support more MIPS CPU names: mips1 - mips5.
llvm-svn: 212338
2014-07-04 12:36:56 +00:00
Simon Atanasyan
6b3544eb1d [Driver][Mips] Check MIPS CPU name provided to the Clang driver.
llvm-svn: 212260
2014-07-03 08:31:23 +00:00
Saleem Abdulrasool
4bddd9d400 CodeGen: make target builtins support languages
This extends the target builtin support to allow language specific annotations
(i.e. LANGBUILTIN).  This is to allow MSVC compatibility whilst retaining the
ability to have EABI targets use a __builtin_ prefix.  This is merely to allow
uniformity in the EABI case where the unprefixed name is provided as an alias in
the header.

llvm-svn: 212196
2014-07-02 17:41:27 +00:00
Tim Northover
1471cb17ae X86: inline all atomic operations up to 128-bits.
The backend *can* cope with all of these now, so Clang should give it the
chance. On CPUs without cmpxchg16b (e.g. the original athlon64) LLVM can reform
the libcalls.

rdar://problem/13496295

llvm-svn: 212173
2014-07-02 10:25:45 +00:00
David Majnemer
f607234fde Driver: Handle /GR- in a compatible way with MSVC
There are slight differences between /GR- and -fno-rtti which made
mapping one to the other inappropriate.

-fno-rtti disables dynamic_cast, typeid, and does not emit RTTI related
information for the v-table.

/GR- does not generate complete object locators and thus will not
reference them in vftables.  However, constructs like dynamic_cast and
typeid are permitted.

This should bring our implementation of RTTI up to semantic parity with
MSVC modulo bugs.

llvm-svn: 212138
2014-07-01 22:24:56 +00:00
Simon Atanasyan
ad80595b60 [Driver][Mips] MIPS ABI names "32" and "64" used as arguments of the "-mabi"
command line option only. Internally we convert them to the "o32" and "n64"
respectively. So we do not need to refer them anywhere after that conversion.

No functional changes.

llvm-svn: 212096
2014-07-01 10:59:09 +00:00
Saleem Abdulrasool
521cec84ac Basic: correct the va_list type on Windows on ARM
Windows on ARM defines va_list as a typedef for char *.  Although the semantics
of argument passing for variadic functions matches AAPCS VFP, the wrapped
struct __va_list type is unused.  This makes the intrinsic definition for
va_list match that of Visual Studio.

llvm-svn: 212004
2014-06-29 23:05:41 +00:00
Saleem Abdulrasool
24bd7da2d2 Basic: fix handling for Windows Itanium environment
This corrects the handling for i686-windows-itanium.  This environment is nearly
identical to Windows MSVC, except it uses the itanium ABI for C++.

llvm-svn: 211991
2014-06-28 23:34:11 +00:00
Saleem Abdulrasool
d1ee08e7cd Basic: whitespace cleanup
Remove unnecessary separation of anonymous namespace.  NFC.

llvm-svn: 211990
2014-06-28 23:34:07 +00:00
Simon Atanasyan
98ba8a657d [Driver][Mips] Fix else-after-return.
No functional changes.

llvm-svn: 211984
2014-06-28 15:56:08 +00:00
Simon Atanasyan
755d7f9c28 [Driver][Mips] Remove redundant brackets.
No functional changes.

llvm-svn: 211983
2014-06-28 15:56:03 +00:00
Simon Atanasyan
9601e6bfaa [Driver][Mips] Remove redundant abstract/override function.
No functional changes.

llvm-svn: 211982
2014-06-28 15:55:55 +00:00
Yi Kong
a44c4d7173 Introduce arm_acle.h supporting existing LLVM builtin intrinsics
Summary: This patch introduces ACLE header file, implementing extensions that can be directly mapped to existing Clang intrinsics. It implements for both AArch32 and AArch64.

Reviewers: t.p.northover, compnerd, rengolin

Reviewed By: compnerd, rengolin

Subscribers: rnk, echristo, compnerd, aemerson, mroth, cfe-commits

Differential Revision: http://reviews.llvm.org/D4296

llvm-svn: 211962
2014-06-27 21:25:42 +00:00
Jim Grosbach
be83cb8c96 ARM: Correctly identify cortex-m4 as v7em.
Get the predefined macro for the architecture correct.
cortex-m4: __ARM_ARCH_7EM__
cortex-m3: __ARM_ARCH_7M__
cortex-m0: __ARM_ARCH_6M__

rdar://17420090

llvm-svn: 211792
2014-06-26 17:24:16 +00:00
Will Schmidt
f048751912 Add ppc64/power8 as a target
llvm-svn: 211778
2014-06-26 13:34:10 +00:00
Matt Arsenault
56f008d538 Add R600 builtin codegen.
llvm-svn: 211631
2014-06-24 20:45:01 +00:00
Saleem Abdulrasool
9d45e77dca Driver: enhance MSC version compatibility
The version information for Visual Studio is spread over multiple variables.
The newer Windows SDK has started making use of some of the extended versioning
variables that were previously undefined.  Enhance our compatibility definitions
for these cases.

_MSC_VER is defined to be the Major * 100 + Minor.  _MSC_FULL_VER is defined to
be Major * 10000000 + Minor * 100000 + Build.  And _MSC_BUILD is the build
revision of the compiler.

Extend the -fmsc-version option in a compatible manner.  If the value is the
previous form of MMmm, then we assume that the build number is 0.  Otherwise, a
specific build number may be passed by using the form MMmmbbbbb.  Due to
bitwidth limitations of the option, it is currently not possible to define a
revision value.

The version information can be passed as either the decimal encoded value
(_MSC_FULL_VER or _MSC_VER) or as a dot-delimited value.

The change to the TextDiagnostic is to deal with the updated encoding of the
version information.

llvm-svn: 211420
2014-06-20 22:58:35 +00:00
Saleem Abdulrasool
0e3258cea8 Preprocessor: improve ACLE 6.4.1, 6.4.2 support
This improves conformance with ACLE 6.4.1.  Define additional macros that
indicate support for the ARM and Thumb instruction set architecture.  This
includes the following set of macros:

  __ARM_ARCH
  __ARM_ARCH_ISA_ARM
  __ARM_ARCH_ISA_THUMB
  __ARM_32BIT_STATE

These help identify the environment that the code is intended to execute on.

Adjust the handling for ACLE 6.4.2 to be more correct.  We would define the
profile as a free-standing token rather than a quoted single character.

llvm-svn: 210991
2014-06-15 18:35:07 +00:00