Chris Lattner
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
Rafael Espindola
c3ed77e1b9
add a "load effective address"
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llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola
bf8e751488
Declare the callee saved regs
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Remove the hard coded store and load of the link register
Implement ARMFrameInfo
llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Rafael Espindola
1c41fc9b06
correctly set LocalAreaOffset of TargetFrameInfo
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llvm-svn: 29589
2006-08-09 17:37:45 +00:00
Rafael Espindola
f5ce475540
fix the spill code
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llvm-svn: 29583
2006-08-09 16:41:12 +00:00
Rafael Espindola
58159b36a3
fix the loading of the link register in emitepilogue
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llvm-svn: 29580
2006-08-09 13:15:47 +00:00
Rafael Espindola
8c41f99e6f
change the addressing mode of the str instruction to reg+imm
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llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola
39083e7836
initial support for variable number of arguments
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llvm-svn: 29567
2006-08-08 13:02:29 +00:00
Rafael Espindola
976c93a110
implemented sub
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correctly update the stack pointer in the prologue and epilogue
llvm-svn: 29244
2006-07-21 12:26:16 +00:00
Rafael Espindola
bf3a17cd32
initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
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llvm-svn: 29175
2006-07-18 17:00:30 +00:00
Rafael Espindola
185c5c2bdf
add the memri memory operand
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this makes it possible for ldr instructions with non-zero immediate
llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola
e40a7e2aa2
create the raddr addressing mode that matches any register and the frame index
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use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot
llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola
f6f5aff038
handle the "mov reg1, reg2" case in isMoveInstr
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llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola
a88966fd5e
initial implementation of ARMRegisterInfo::eliminateFrameIndex
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fixes test/Regression/CodeGen/ARM/ret_arg5.ll
llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Rafael Espindola
b15597b59a
implement movri
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add a stub LowerFORMAL_ARGUMENTS
llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Evan Cheng
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
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llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Rafael Espindola
ffdc24b847
added a skeleton of the ARM backend
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llvm-svn: 28301
2006-05-14 22:18:28 +00:00
