165 Commits

Author SHA1 Message Date
Andrew Trick
ed20075d19 mi-sched: Force bottom up scheduling for generic targets.
Fast register pressure tracking currently only takes effect during
bottom up scheduling. Forcing this is a bit faster and simpler for
targets that don't have many scheduling constraints and don't need
top-down scheduling.

llvm-svn: 190014
2013-09-04 23:54:00 +00:00
Andrew Trick
b05db8e0b9 comment typo
llvm-svn: 189997
2013-09-04 21:12:05 +00:00
Andrew Trick
2a749ee0b9 Remove dead subtree limit code.
llvm-svn: 189995
2013-09-04 21:00:20 +00:00
Andrew Trick
856ecd9ab3 -view-misched-dags, better pruning.
llvm-svn: 189994
2013-09-04 21:00:18 +00:00
Andrew Trick
ef54c59490 mi-sched: DEBUG cleanup, call tracePick for unidirectional scheduling.
llvm-svn: 189993
2013-09-04 21:00:16 +00:00
Andrew Trick
1ab16d9ecf 80 columns
llvm-svn: 189992
2013-09-04 21:00:13 +00:00
Andrew Trick
66c3dfbf8c mi-sched: Suppress register pressure tracking when the scheduling window is too small.
If the instruction window is < NumRegs/2, pressure tracking is not
likely to be effective. The scheduler has to process a very large
number of tiny blocks. We want this to be fast.

llvm-svn: 189991
2013-09-04 21:00:11 +00:00
Andrew Trick
a6e877707f mi-sched: Load clustering is a bit to expensive to enable unconditionally.
llvm-svn: 189990
2013-09-04 21:00:08 +00:00
Andrew Trick
8c699c93b2 mi-sched: Reuse an invalid HazardRecognizer to save compile time.
llvm-svn: 189989
2013-09-04 21:00:05 +00:00
Andrew Trick
310190e21f mi-sched: bypass heuristic checks when regpressure tracking is disabled.
llvm-svn: 189988
2013-09-04 21:00:02 +00:00
Andrew Trick
b6e74712b6 Added -misched-regpressure option.
Register pressure tracking is half the complexity of the
scheduler. It's useful to be able to turn it off for compile time and
performance comparisons.

llvm-svn: 189987
2013-09-04 20:59:59 +00:00
Andrew Trick
2c4f8b7ee8 Fix my previous checkin to updatePressureDiffs.
There was one case that we could hit a DebugValue where I didn't think
to check. DebugValues are evil. No checkinable test case, sorry. It's
an obvious fix.

llvm-svn: 189717
2013-08-31 05:17:58 +00:00
Andrew Trick
2bc74c2887 mi-sched: update PressureDiffs on-the-fly for liveness.
This removes all expensive pressure tracking logic from the scheduling
critical path of node comparison.

llvm-svn: 189643
2013-08-30 04:36:57 +00:00
Andrew Trick
b1a45b6c61 mi-sched: improve the generic register pressure comparison.
Only compare pressure within the same set. When multiple sets are
affected, we prioritize the most constrained set.

llvm-svn: 189641
2013-08-30 04:27:29 +00:00
Andrew Trick
1a8313458f mi-sched: Precompute a PressureDiff for each instruction, adjust for liveness later.
Created SUPressureDiffs array to hold the per node PDiff computed during DAG building.

Added a getUpwardPressureDelta API that will soon replace the old
one. Compute PressureDelta here from the precomputed PressureDiffs.

Updating for liveness will come next.

llvm-svn: 189640
2013-08-30 03:49:48 +00:00
Andrew Trick
ef80f50058 comment typo
llvm-svn: 189635
2013-08-30 02:02:12 +00:00
Andrew Trick
483f4199f3 Comment and revise the cyclic critical path code.
This should be much more clear now. It's still disabled pending testing.

llvm-svn: 189597
2013-08-29 18:04:49 +00:00
Andrew Trick
c01b00400d Adds cyclic critical path computation and heuristics, temporarily disabled.
Estimate the cyclic critical path within a single block loop. If the
acyclic critical path is longer, then the loop will exhaust OOO
resources after some number of iterations. If lag between the acyclic
critical path and cyclic critical path is longer the the time it takes
to issue those loop iterations, then aggressively schedule for
latency.

llvm-svn: 189120
2013-08-23 17:48:43 +00:00
Andrew Trick
a53e101627 mi-sched: Don't call MBB.size() in initSUnits. The driver already has instr count.
This fixes a pathological compile time problem with very large blocks
and lots of scheduling boundaries.

llvm-svn: 189116
2013-08-23 17:48:33 +00:00
Andrew Trick
2f7667e018 Confusing comment typo.
llvm-svn: 187895
2013-08-07 17:20:32 +00:00
Andrew Trick
9c17eab761 MI Sched: Track live-thru registers.
When registers must be live throughout the scheduling region, increase
the limit for the register class. Once we exceed the original limit,
they will be spilled, and there's no point further reducing pressure.

This isn't a perfect heuristics but avoids a situation where the
scheduler could become trapped by trying to achieve the impossible.

llvm-svn: 187436
2013-07-30 19:59:12 +00:00
Andrew Trick
d9761776bc MI Sched fix: assert "Disconnected LRG within the scheduling region."
llvm-svn: 187435
2013-07-30 19:59:08 +00:00
Andrew Trick
401b6959ae MI Sched: Register pressure heuristics.
Consider which set is being increased or decreased before comparing.

llvm-svn: 187110
2013-07-25 07:26:35 +00:00
Andrew Trick
9706496b0d Dump LIS before regalloc. MI sched changes them.
llvm-svn: 187107
2013-07-25 07:26:26 +00:00
Alexey Samsonov
64c391dbe4 Fix uninitialized memory read found by MemorySanitizer: always set output parameter of ConvergingScheduler::SchedBoundary::getOtherResourceCount
llvm-svn: 186658
2013-07-19 08:55:18 +00:00
Andrew Trick
b13ef17a14 MI Sched: Update the way resources are tracked so the current heuristics make more sense.
llvm-svn: 186632
2013-07-19 00:20:07 +00:00
Andrew Trick
b55db58edf MI-Sched: cleanup DEBUG output.
llvm-svn: 184565
2013-06-21 18:33:01 +00:00
Andrew Trick
736dd9a255 MI-Sched: Adjust regpressure limits for reserved regs.
llvm-svn: 184564
2013-06-21 18:32:58 +00:00
Andrew Trick
71f08a3e74 Give RegMax higher priority.
llvm-svn: 184133
2013-06-17 21:45:13 +00:00
Andrew Trick
3c3a40e4c6 Remove compareRPDelta.
A complex, expensive heuristic with little value in the current design.

llvm-svn: 184132
2013-06-17 21:45:11 +00:00
Andrew Trick
7e63046ce9 MI-Sched: Remove another heuristic that is sensitive to queue order.
llvm-svn: 184130
2013-06-17 21:45:07 +00:00
Andrew Trick
d40d0f2c1b MI-Sched: Track multiple candidates with the same priority level.
This eliminates the MultiPressure scheduling "reason". It was
sensitive to queue order. We don't like being sensitive to queue
order.

llvm-svn: 184129
2013-06-17 21:45:05 +00:00
Andrew Trick
8e8415f5ab Missing NDEBUGs.
llvm-svn: 184039
2013-06-15 05:46:47 +00:00
Andrew Trick
f78e7fa140 MI-Sched: heuristics using the new latency and machine model.
llvm-svn: 184038
2013-06-15 05:39:19 +00:00
Andrew Trick
de2109eb4c Machine Model: Add MicroOpBufferSize and resource BufferSize.
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

llvm-svn: 184032
2013-06-15 04:49:57 +00:00
Andrew Trick
e2ff575bb8 MI-Sched: Rename IssueCount to CurrMOps.
"Counts" refer to scaled resource counts within a region. CurrMOps is
simply the number of micro-ops to be issue in the current cycle.

llvm-svn: 184031
2013-06-15 04:49:49 +00:00
Andrew Trick
0cd8afc547 MI-Sched: Remove the temporary EnableCopyConstrain flag.
llvm-svn: 184030
2013-06-15 04:49:46 +00:00
Andrew Trick
f5b8ef2690 MI-Sched: added tracking of dependent latency for better heuristics.
Heuristics compare the critical path in the scheduled code, called
ExpectedLatency, with the latency of instructions remaining to be
scheduled. There are two ways to look at remaining latency:

(1) Dependent latency includes the latency between unscheduled and
scheduled instructions.

(2) Independent latency is simply the height (bottom-up) or depth
(top-down) of instructions currently in the ready Q.

llvm-svn: 184029
2013-06-15 04:49:44 +00:00
Andrew Trick
5580e5ca80 MI-Sched: DEBUG: print critical resource.
llvm-svn: 184028
2013-06-15 04:49:42 +00:00
Jakub Staszak
80df8b837f Move #include from .h to .cpp file.
llvm-svn: 183960
2013-06-14 00:00:13 +00:00
Andrew Trick
dd77014acc MI Sched: revert a minor heuristic that snuck in with -misched-vcopy.
I'll fix the heuristic in a general way in a follow-up commit.

llvm-svn: 180815
2013-04-30 22:10:59 +00:00
Andrew Trick
2e87517144 Fix for r180193 - MI Sched: eliminate local vreg.
Fixes PR15838. Need to check for blocks with nothing but dbg.value.

I'm not sure how to force this situation with a unit test. I tried to
reduce the test case in PR15838 (1k lines of metadata) but gave up.

llvm-svn: 180227
2013-04-24 23:19:56 +00:00
Andrew Trick
85a1d4cbc0 MI Sched: eliminate local vreg copies.
For now, we just reschedule instructions that use the copied vregs and
let regalloc elliminate it. I would really like to eliminate the
copies on-the-fly during scheduling, but we need a complete
implementation of repairIntervalsInRange() first.

The general strategy is for the register coalescer to eliminate as
many global copies as possible and shrink live ranges to be
extended-basic-block local. The coalescer should not have to worry
about resolving local copies (e.g. it shouldn't attemp to reorder
instructions). The scheduler is a much better place to deal with local
interference. The coalescer side of this equation needs work.

llvm-svn: 180193
2013-04-24 15:54:43 +00:00
Andrew Trick
7c791a3dc4 MI Sched: regpressure tracing.
llvm-svn: 180191
2013-04-24 15:54:36 +00:00
Andrew Trick
1f0bb69b6c MI-Sched: DEBUG formatting.
llvm-svn: 179452
2013-04-13 06:07:49 +00:00
Andrew Trick
e833e1cd6e MI-Sched: schedule physreg copies.
The register allocator expects minimal physreg live ranges. Schedule
physreg copies accordingly. This is slightly tricky when they occur in
the middle of the scheduling region. For now, this is handled by
rescheduling the copy when its associated instruction is
scheduled. Eventually we may instead bundle them, but only if we can
preserve the bundles as parallel copies during regalloc.

llvm-svn: 179449
2013-04-13 06:07:40 +00:00
Andrew Trick
80e66ce0b4 RegisterPressure heuristics currently require signed comparisons.
llvm-svn: 178823
2013-04-05 00:31:34 +00:00
Andrew Trick
96ce3848d6 Disable DFSResult for ConvergingScheduler.
For now, just save the compile time since the ConvergingScheduler
heuristics don't use this analysis. We'll probably enable it later
after compile-time investigation.

llvm-svn: 178822
2013-04-05 00:31:31 +00:00
Andrew Trick
419d491747 MachineScheduler: format DEBUG output.
I'm getting more serious about tuning and enabling on x86/ARM. Start
by making the trace readable.

llvm-svn: 178821
2013-04-05 00:31:29 +00:00
Matt Arsenault
4ab769f4b3 Fix missing std::. Not sure how this compiles for anyone else.
llvm-svn: 177620
2013-03-21 00:57:21 +00:00