65 Commits

Author SHA1 Message Date
Kevin Enderby
014e1cde5f Fix the x86 disassembler to at least print the lock prefix if it is the first
prefix.  Added a FIXME to remind us this still does not work when it is not the
first prefix.

llvm-svn: 152414
2012-03-09 17:52:49 +00:00
Craig Topper
6491c8020e X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
llvm-svn: 151510
2012-02-27 01:54:29 +00:00
Craig Topper
66a3597a4a Add vmfunc instruction to X86 assembler and disassembler.
llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Craig Topper
ed7aa46366 Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Craig Topper
2ba766ae84 Add disassembler support for VPERMIL2PD and VPERMIL2PS.
llvm-svn: 147368
2011-12-30 06:23:39 +00:00
Craig Topper
03a0beda88 Add FMA4 instructions to disassembler.
llvm-svn: 147367
2011-12-30 05:20:36 +00:00
Craig Topper
75ffc5fbb5 Remove some unnecessary filtering checks from X86 disassembler table build.
llvm-svn: 144986
2011-11-19 05:48:20 +00:00
Craig Topper
f01f1b5cb9 More AVX2 instructions and their intrinsics.
llvm-svn: 143895
2011-11-06 23:04:08 +00:00
Craig Topper
980d59832a Add X86 RORX instruction
llvm-svn: 142741
2011-10-23 07:34:00 +00:00
Craig Topper
96fa597828 Add X86 PEXTR and PDEP instructions.
llvm-svn: 142141
2011-10-16 16:50:08 +00:00
Craig Topper
aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection.
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Craig Topper
0ae8d4d738 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
llvm-svn: 142117
2011-10-16 07:05:40 +00:00
Craig Topper
25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
Craig Topper
27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Craig Topper
965de2c197 Add X86 ANDN instruction. Including instruction selection.
llvm-svn: 141947
2011-10-14 07:06:56 +00:00
Craig Topper
a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
llvm-svn: 141642
2011-10-11 04:34:23 +00:00
Craig Topper
23eb468b1f Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
llvm-svn: 141274
2011-10-06 06:44:41 +00:00
Craig Topper
f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
llvm-svn: 141065
2011-10-04 06:30:42 +00:00
Craig Topper
d07a59f288 Fix disassembling of INVEPT and INVVPID to take operands
llvm-svn: 140955
2011-10-01 21:20:14 +00:00
Craig Topper
88cb33e0d4 Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
llvm-svn: 140954
2011-10-01 19:54:56 +00:00
Craig Topper
526adabe87 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700.
llvm-svn: 140370
2011-09-23 06:57:25 +00:00
Craig Topper
ee8157cb41 Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
llvm-svn: 139691
2011-09-14 06:41:26 +00:00
Craig Topper
e98d8a5c84 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
llvm-svn: 139588
2011-09-13 06:54:58 +00:00
Craig Topper
a88e356017 Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
llvm-svn: 139485
2011-09-11 21:41:45 +00:00
Craig Topper
a948cb9058 Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
llvm-svn: 139484
2011-09-11 20:23:20 +00:00
Kevin Enderby
54e09b4799 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702.
llvm-svn: 139014
2011-09-02 18:03:03 +00:00
Craig Topper
4f2fba1108 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
llvm-svn: 138795
2011-08-30 07:09:35 +00:00
Kevin Enderby
7e2489a7c9 Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
llvm-svn: 138771
2011-08-29 22:06:28 +00:00
David Greene
af8ee2cdee Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00
David Greene
1aa0e3e118 [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
Kevin Enderby
5ef6c453a6 Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
    pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored.  The others remain unchanged.

llvm-svn: 136287
2011-07-27 23:01:50 +00:00
Eli Friedman
0318036c4d Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
llvm-svn: 135337
2011-07-16 02:41:28 +00:00
Eric Christopher
71520a867d Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene
af973b4f36 [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Joerg Sonnenberger
fc4789da4a Add support for the VIA PadLock instructions.
llvm-svn: 128826
2011-04-04 16:58:13 +00:00
Sean Callanan
c3fd523731 X86 table-generator and disassembler support for the AVX
instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.

llvm-svn: 127644
2011-03-15 01:23:15 +00:00
Rafael Espindola
e39062199e Implement xgetbv and xsetbv.
Patch by Jai Menon.

llvm-svn: 126165
2011-02-22 00:35:18 +00:00
Owen Anderson
578074b2f3 In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

llvm-svn: 121710
2010-12-13 19:31:11 +00:00
Chris Lattner
d8adec70f3 factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
2010-11-01 04:03:32 +00:00
Kevin Enderby
5e7cb5fc27 Added the x86 instruction ud2b (2nd official undefined instruction).
llvm-svn: 117485
2010-10-27 20:46:49 +00:00
Sean Callanan
8d302b2e71 Fixed the disassembler to handle two new X86
instruction forms.  Now the ENTER instruction
disassembles correctly.

llvm-svn: 115573
2010-10-04 22:45:51 +00:00
Dale Johannesen
dd224d2333 Massive rewrite of MMX:
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.

Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics. 

MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces.  Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.

The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.

llvm-svn: 115243
2010-09-30 23:57:10 +00:00
Chris Lattner
f60062fd55 add basic avx support to the disassembler, also teach it about ssmem/sdmem
operands.

With this done, we can remove the _Int suffixes from the round instructions
without the disassembler blowing up.  This allows the assembler to support
them, implementing rdar://8456376 - llvm-mc rejects 'roundss'

llvm-svn: 115019
2010-09-29 02:57:56 +00:00
Dale Johannesen
605acfe533 Add patterns for MMX that use the new intrinsics.
Enable palignr intrinsic.
These may need adjustment for a new VT in due course.

llvm-svn: 113233
2010-09-07 18:10:56 +00:00
Duncan Sands
41b4a6b36a Convert some tab stops into spaces.
llvm-svn: 108130
2010-07-12 08:16:59 +00:00
Chris Lattner
ac5881295c Implement the major chunk of PR7195: support for 'callw'
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
fd5458d4bd More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm)
Introduce the VEX_X field

llvm-svn: 105859
2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes
c2f87b7bb2 Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.

llvm-svn: 105652
2010-06-08 22:51:23 +00:00
Chris Lattner
fdd2614330 revert r105521, which is breaking the buildbots with stuff like this:
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
594fa26317 Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.

llvm-svn: 105521
2010-06-05 03:53:24 +00:00