689 Commits

Author SHA1 Message Date
Joerg Sonnenberger
fbd51bef13 Assume ARMv6 for NetBSD for now for strex/ldrex.
llvm-svn: 196115
2013-12-02 16:12:05 +00:00
Joerg Sonnenberger
7c7fcec329 NetBSD uses long derived size_t / ssize_t in all ARM ABIs.
llvm-svn: 196114
2013-12-02 16:09:34 +00:00
Joerg Sonnenberger
84c7ca8851 NetBSD uses signed wchar_t on ARM platforms.
llvm-svn: 195970
2013-11-30 00:38:16 +00:00
Richard Barton
3b82ed3948 Add support for Cortex-A12.
Patch by Oliver Stannard!

llvm-svn: 195449
2013-11-22 11:53:28 +00:00
Tim Northover
5bb34ca4df ARM: define & use __ARM_NEON on ARM32 (as per ACLE)
There seem to be quite a few references to the old macro __ARM_NEON__ on the
internet, so I don't think it's a good idea to remove it entirely (at least
yet), but the canonical name does not have the trailing underscores so we
should use that ourselves.

llvm-svn: 195353
2013-11-21 12:36:34 +00:00
Jim Grosbach
e2bfac497d ARM: embedded v7 'darwin' doesn't get min-version defines.
Make sure armv7 doesn't get the iOS deployment version definitions when
it's being used for non-iOS.

rdar://15497681

llvm-svn: 195149
2013-11-19 20:18:39 +00:00
Jiangning Liu
c8b0a1ad95 Clean up predefined macros for AArch64 to follow ACLE 2.0.
llvm-svn: 195068
2013-11-19 01:33:17 +00:00
Tom Stellard
5558304ba2 R600: Add processor type for Hawaii
llvm-svn: 194751
2013-11-14 23:45:53 +00:00
Daniel Sanders
8b59af15ed [mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.

llvm-svn: 194476
2013-11-12 12:56:01 +00:00
Robert Lytton
cc4246614f XCore target Type defines.
Change SizeType, PtrDiffType, IntPtrType, WCharType, WIntType
to follow the XMOS llvm-gcc front end's settings.

llvm-svn: 194461
2013-11-12 10:09:30 +00:00
Akira Hatanaka
c4baedd71d [mips] Partially revert r193640. Stack alignment should not be determined by
the floating point register mode.

llvm-svn: 194426
2013-11-11 22:10:46 +00:00
Tim Northover
e77f78cbad Darwin(ish): we don't want __ARM_EABI__ even on v7a embedded targets.
llvm-svn: 194408
2013-11-11 19:11:22 +00:00
Joerg Sonnenberger
0e921f2bd9 NetBSD 6.99.26 switched to default rounding mode, so adjust
__FLT_EVAL_METHOD__ accordingly. Add test case for this and the SSE2
variances on NetBSD.

llvm-svn: 194377
2013-11-11 14:00:37 +00:00
Benjamin Kramer
d9a5e2a490 Driver: Add support for -march=bdver3 on x86.
llvm-svn: 193985
2013-11-04 10:29:51 +00:00
Amara Emerson
703da2ea98 [AArch64] Add some CPU targets for "generic", A-53 and A-57.
Enables the clang driver to begin targeting specific CPUs. Introduced a
"generic" CPU which will ensure that the optional FP feature is enabled
by default when it gets to LLVM, without needing any extra arguments.
Cortex-A53 and A-57 are also introduced with tests, although backend
handling of them does not yet exist.

llvm-svn: 193740
2013-10-31 09:32:33 +00:00
Akira Hatanaka
babd67e6ce [mips] Delete unused functions.
llvm-svn: 193674
2013-10-30 02:38:17 +00:00
Akira Hatanaka
618b29813a [mips] Align the stack to 16-bytes for -mfp64.
llvm-svn: 193640
2013-10-29 19:00:35 +00:00
Akira Hatanaka
9064e36551 [mips] Move setDescriptionString to base class MipsTargetInfoBase and call it
at the end of handleTargetFeatures.

No intended functionality change.

llvm-svn: 193636
2013-10-29 18:30:33 +00:00
Tom Stellard
08ded12ffb R600: Add Sea Islands GPUs
llvm-svn: 193622
2013-10-29 16:38:29 +00:00
Bernard Ogden
18b5701a68 ARM: Add -m[no-]crc to dis/enable CRC subtargetfeature from clang
Allow users to disable or enable CRC subtarget feature.

Differential Revision: http://llvm-reviews.chandlerc.com/D2037

llvm-svn: 193600
2013-10-29 09:47:51 +00:00
Bernard Ogden
da13af380a Add driver support for FP, SIMD and crypto defaults.
Although we wire up a bit for v8fp for macro setting
purposes, we don't set a macro yet. Need to ask list
about that.

Change-Id: Ic9819593ce00882fbec72757ffccc6f0b18160a0
llvm-svn: 193367
2013-10-24 18:32:51 +00:00
Bernard Ogden
58a05cff97 Clean up char/numeric comparisons in ARM getTargetDefines
Change-Id: Ie07228411b68252adcd5cf80b27ccd2eb3b031d9
llvm-svn: 193366
2013-10-24 18:32:44 +00:00
Bernard Ogden
021d7dacd0 Teach clang driver about Cortex-A53 and Cortex-A57.
Adds some Cortex-A53 strings where they were missing before.
Cortex-A57 is entirely new to clang.

Doesn't touch code only used by Darwin, in consequence of which
one of the A53 lines has been removed.

Change-Id: I5edb58f6eae93947334787e26a8772c736de6483
llvm-svn: 193364
2013-10-24 18:32:36 +00:00
Tim Northover
901dee4d28 ARM-Darwin: Use the *-*-darwin-eabi triple for v6m & v7m archs
These arch arguments are used for embedded targets (obviously) which need a
different calling convention to iOS.

llvm-svn: 193328
2013-10-24 10:48:50 +00:00
Silviu Baranga
e5690463e2 Set the default hardware division features for ARM cpus. Also set it as default for A32 armv8.
llvm-svn: 193075
2013-10-21 10:59:33 +00:00
Silviu Baranga
f9671dd09d Add the __ARM_ARCH_EXT_IDIV__ predefine. It is set to 1 if we have hardware divide in the mode that we are compiling in (depending on the target features), not defined if we don't. Should be compatible with the GCC conterpart. Also adding a -hwdiv option to overide the default behavior.
llvm-svn: 193074
2013-10-21 10:54:53 +00:00
Simon Atanasyan
2c97a81e81 [Mips] Define __mips_fpr and _MIPS_FPSET macros.
llvm-svn: 192969
2013-10-18 13:13:53 +00:00
Eric Christopher
3ff21b3195 Rename HandleTargetFeatures->handleTargetFeatures to match
everything else in the class.

llvm-svn: 192851
2013-10-16 21:26:26 +00:00
Eric Christopher
2fe3b4a490 Add preprocessor support for powerpc vsx.
The test should be expanded upon for more powerpc checking.

llvm-svn: 192849
2013-10-16 21:19:26 +00:00
Eric Christopher
c04fe09c1d Fix comments.
llvm-svn: 192847
2013-10-16 21:19:19 +00:00
Yunzhong Gao
6108936fa6 Enabling 3DNow! prefetch instruction support for a few AMD processors in the
clang front end. This change will allow the __PRFCHW__ macro to be set on these
processors and hence include prfchwintrin.h in x86intrin.h header. Support for
the intrinsic itself seems to have already been added in r178041.

Differential Revision: http://llvm-reviews.chandlerc.com/D1934

llvm-svn: 192829
2013-10-16 19:07:02 +00:00
Nick Lewycky
50e8f480ea Add support for -mcx16, and predefine __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 when
it is enabled. Also enable it on the same architectures that GCC does.

llvm-svn: 192045
2013-10-05 20:14:27 +00:00
Weiming Zhao
53a797ce7b Fix PR 12730: Add _GCC_HAVE_SYNC_COMPARE_AND_SWAP macros for ARM
llvm-svn: 191707
2013-09-30 22:51:32 +00:00
Ed Schouten
d062146896 Add character set related __STDC_* definitions.
Clang uses UTF-16 and UTF-32 for its char16_t's and char32_t's
exclusively. This means that we can define __STDC_UTF_16__ and
__STDC_UTF_32__ unconditionally.

While there, define __STDC_MB_MIGHT_NEQ_WC__ for FreeBSD. FreeBSD's
wchar_t's don't encode characters as ISO-10646; the encoding depends on
the locale used. Because the character set used might not be a superset
of ASCII, we must define __STDC_MB_MIGHT_NEQ_WC__.

llvm-svn: 191631
2013-09-29 07:54:52 +00:00
Yunzhong Gao
1f6aeebe76 Adding -mtbm and -mno-tbm command line options to the clang front end for the
x86 TBM instruction set. Also adding a __TBM__ macro if the TBM feature is
enabled. Otherwise there should be no functionality change to existing features.

Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1693

llvm-svn: 191326
2013-09-24 19:00:58 +00:00
Simon Atanasyan
22127cee34 [Mips] Support -mnan=2008 option. Define "__mips_nan2008" macros and pass
this option to the assembler.

llvm-svn: 191282
2013-09-24 09:09:16 +00:00
Petar Jovanovic
c19a284182 [Mips] Allocate NaClTargetInfo for MIPSEL NaCl
A patch to AllocateTarget function to recognize llvm::Triple::NaCl for
MIPSEL and return NaClTargetInfo. Additional test has been added to check
if the expected macros get defined.

llvm-svn: 191124
2013-09-21 01:27:01 +00:00
Ben Langmuir
58078d0103 Add C intrinsics for Intel SHA Extensions
Intrinsics added shaintrin.h, which is included from x86intrin.h if __SHA__ is
enabled. SHA implies SSE2, which is needed for the __m128i type.

Also add the -msha/-mno-sha option.

llvm-svn: 190999
2013-09-19 13:22:04 +00:00
Craig Topper
2956112308 Use curly braces all the way through long if/else chain for consistency and readability.
llvm-svn: 190982
2013-09-19 01:13:07 +00:00
Craig Topper
5f79e2661d Disabling sse2 should disable aes and pclmul support.
llvm-svn: 190977
2013-09-19 00:01:05 +00:00
Joey Gouly
1e8637b259 [ARMv8] Add builtins for CRC instructions.
Patch by Bradley Smith!

llvm-svn: 190931
2013-09-18 10:07:09 +00:00
Craig Topper
86d79ef4b8 Push contents of X86TargetInfo::setFeatureEnabled down to a static function called by the virtual version and all the places in getDefaultFeatures. This way getDefaultFeatures doesn't make so many virtual calls.
llvm-svn: 190847
2013-09-17 04:51:29 +00:00
Craig Topper
13f61a6c37 Mark setSSELevel/setMMXLevel/setXOPLevel as static since they don't access anything in the class.
llvm-svn: 190846
2013-09-17 04:12:55 +00:00
Amara Emerson
8c3de546d6 Add error checking to reject neon_vector_type attribute on targets without NEON.
Patch by Artyom Skrobov.

llvm-svn: 190801
2013-09-16 18:07:35 +00:00
Craig Topper
31db3a2efc Make F16C feature imply AVX. Matches GCC behavior.
llvm-svn: 190776
2013-09-16 04:54:13 +00:00
Cameron Esfahani
556d91e2c3 Clean up some Triple usage in clang.
llvm-svn: 190737
2013-09-14 01:09:11 +00:00
Preston Gurd
a3c58c02f1 Update Atom Silvermont (SLM) support by adding enabled features.
llvm-svn: 190718
2013-09-13 19:27:17 +00:00
Renato Golin
1a04f22356 Add more Cortex CPUs and tests
llvm-svn: 190703
2013-09-13 17:02:54 +00:00
Renato Golin
eefb577be8 Fix Neon detection for Cortex-A class, plus adds some more CPUs to default features
llvm-svn: 190702
2013-09-13 17:02:45 +00:00
David Tweed
31d09b0cef Certain multi-platform languages, such as OpenCL, have the concept of
address spaces which is both (1) a "semantic" concept and
(2) possibly a hardware level restriction. It is desirable to
be able to discard/merge the LLVM-level address spaces on arguments for which
there is no difference to the current backend while keeping
track of the semantic address spaces in a funciton prototype. To do this
enable addition of the address space into the name-mangling process. Add
some tests to document this behaviour against inadvertent changes.

Patch by Michele Scandale!

llvm-svn: 190684
2013-09-13 12:04:22 +00:00