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63ca93c7d1
This patch renames the `OpenMPIRBuilderConfig` flags to reduce confusion over their meaning. `IsTargetCodegen` becomes `IsGPU`, whereas `IsEmbedded` becomes `IsTargetDevice`. The `-fopenmp-is-device` compiler option is also renamed to `-fopenmp-is-target-device` and the `omp.is_device` MLIR attribute is renamed to `omp.is_target_device`. Getters and setters of all these renamed properties are also updated accordingly. Many unit tests have been updated to use the new names, but an alias for the `-fopenmp-is-device` option is created so that external programs do not stop working after the name change. `IsGPU` is set when the target triple is AMDGCN or NVIDIA PTX, and it is only valid if `IsTargetDevice` is specified as well. `IsTargetDevice` is set by the `-fopenmp-is-target-device` compiler frontend option, which is only added to the OpenMP device invocation for offloading-enabled programs. Differential Revision: https://reviews.llvm.org/D154591
100 lines
6.1 KiB
C
100 lines
6.1 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -internal-isystem %S/Inputs/include -x c -fopenmp -fopenmp-targets=amdgcn-amd-amdhsa -triple powerpc64le-unknown-unknown -D__OFFLOAD_ARCH_gfx90a__ -emit-llvm-bc %s -o %t-host.bc
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// RUN: %clang_cc1 -include __clang_hip_runtime_wrapper.h -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/../../lib/Headers/openmp_wrappers -internal-isystem %S/Inputs/include -x c -fopenmp -triple amdgcn-amd-amdhsa -aux-triple x86_64-unknown-unknown -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-target-device -fopenmp-host-ir-file-path %t-host.bc -o - | FileCheck %s --check-prefixes=CHECK
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// REQUIRES: amdgpu-registered-target
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#include <stdlib.h>
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#pragma omp begin declare target
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// CHECK-LABEL: @test_math_int(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[__SGN_I:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[L1:%.*]] = alloca i32, align 4, addrspace(5)
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// CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr
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// CHECK-NEXT: [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr
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// CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[X_ADDR_ASCAST]], align 4
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// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
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// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr
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// CHECK-NEXT: [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr
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// CHECK-NEXT: store i32 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 4
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// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[__X_ADDR_ASCAST_I]], align 4
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// CHECK-NEXT: [[SHR_I:%.*]] = ashr i32 [[TMP1]], 31
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// CHECK-NEXT: store i32 [[SHR_I]], ptr [[__SGN_ASCAST_I]], align 4
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// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[__X_ADDR_ASCAST_I]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[__SGN_ASCAST_I]], align 4
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// CHECK-NEXT: [[XOR_I:%.*]] = xor i32 [[TMP2]], [[TMP3]]
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// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[__SGN_ASCAST_I]], align 4
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// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw i32 [[XOR_I]], [[TMP4]]
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// CHECK-NEXT: store i32 [[SUB_I]], ptr [[L1_ASCAST]], align 4
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// CHECK-NEXT: ret void
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//
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void test_math_int(int x) {
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int l1 = abs(x);
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}
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// CHECK-LABEL: @test_math_long(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[__SGN_I:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[L1:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr
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// CHECK-NEXT: [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr
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// CHECK-NEXT: store i64 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
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// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr
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// CHECK-NEXT: [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr
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// CHECK-NEXT: store i64 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
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// CHECK-NEXT: [[SHR_I:%.*]] = ashr i64 [[TMP1]], 63
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// CHECK-NEXT: store i64 [[SHR_I]], ptr [[__SGN_ASCAST_I]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
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// CHECK-NEXT: [[XOR_I:%.*]] = xor i64 [[TMP2]], [[TMP3]]
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
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// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw i64 [[XOR_I]], [[TMP4]]
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// CHECK-NEXT: store i64 [[SUB_I]], ptr [[L1_ASCAST]], align 8
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// CHECK-NEXT: ret void
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//
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void test_math_long(long x) {
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long l1 = labs(x);
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}
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// CHECK-LABEL: @test_math_long_long(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[RETVAL_I:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[__X_ADDR_I:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[__SGN_I:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[X_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[L1:%.*]] = alloca i64, align 8, addrspace(5)
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// CHECK-NEXT: [[X_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[X_ADDR]] to ptr
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// CHECK-NEXT: [[L1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[L1]] to ptr
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// CHECK-NEXT: store i64 [[X:%.*]], ptr [[X_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[X_ADDR_ASCAST]], align 8
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// CHECK-NEXT: [[RETVAL_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL_I]] to ptr
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// CHECK-NEXT: [[__X_ADDR_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__X_ADDR_I]] to ptr
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// CHECK-NEXT: [[__SGN_ASCAST_I:%.*]] = addrspacecast ptr addrspace(5) [[__SGN_I]] to ptr
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// CHECK-NEXT: store i64 [[TMP0]], ptr [[__X_ADDR_ASCAST_I]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
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// CHECK-NEXT: [[SHR_I:%.*]] = ashr i64 [[TMP1]], 63
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// CHECK-NEXT: store i64 [[SHR_I]], ptr [[__SGN_ASCAST_I]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[__X_ADDR_ASCAST_I]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
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// CHECK-NEXT: [[XOR_I:%.*]] = xor i64 [[TMP2]], [[TMP3]]
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// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[__SGN_ASCAST_I]], align 8
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// CHECK-NEXT: [[SUB_I:%.*]] = sub nsw i64 [[XOR_I]], [[TMP4]]
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// CHECK-NEXT: store i64 [[SUB_I]], ptr [[L1_ASCAST]], align 8
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// CHECK-NEXT: ret void
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//
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void test_math_long_long(long long x) {
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long long l1 = llabs(x);
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}
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#pragma omp end declare target
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