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63ca93c7d1
This patch renames the `OpenMPIRBuilderConfig` flags to reduce confusion over their meaning. `IsTargetCodegen` becomes `IsGPU`, whereas `IsEmbedded` becomes `IsTargetDevice`. The `-fopenmp-is-device` compiler option is also renamed to `-fopenmp-is-target-device` and the `omp.is_device` MLIR attribute is renamed to `omp.is_target_device`. Getters and setters of all these renamed properties are also updated accordingly. Many unit tests have been updated to use the new names, but an alias for the `-fopenmp-is-device` option is created so that external programs do not stop working after the name change. `IsGPU` is set when the target triple is AMDGCN or NVIDIA PTX, and it is only valid if `IsTargetDevice` is specified as well. `IsTargetDevice` is set by the `-fopenmp-is-target-device` compiler frontend option, which is only added to the OpenMP device invocation for offloading-enabled programs. Differential Revision: https://reviews.llvm.org/D154591
175 lines
11 KiB
C++
175 lines
11 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
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// RUN: %clang_cc1 -std=c++03 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/Inputs/include -verify -fopenmp -x c++ -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm -fopenmp-is-target-device -o - %s | FileCheck -check-prefixes=NVPTX,NVPTX-CXX03 %s
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// RUN: %clang_cc1 -std=c++11 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/Inputs/include -verify -fopenmp -x c++ -triple nvptx64-nvidia-cuda -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm -fopenmp-is-target-device -o - %s | FileCheck -check-prefixes=NVPTX,NVPTX-NVPTX-CXX11 %s
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// RUN: %clang_cc1 -std=c++03 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/Inputs/include -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm -fopenmp-is-target-device -o - %s | FileCheck -check-prefixes=AMDGPU,AMDGPU-CXX03 %s
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// RUN: %clang_cc1 -std=c++11 -internal-isystem %S/../../lib/Headers/openmp_wrappers -include __clang_openmp_device_functions.h -internal-isystem %S/Inputs/include -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm -fopenmp-is-target-device -o - %s | FileCheck -check-prefixes=AMDGPU,AMDGPU-CXX11 %s
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// expected-no-diagnostics
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#include <new>
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#pragma omp begin declare target
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extern const std::nothrow_t nothrow;
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// NVPTX-LABEL: define hidden noundef ptr @_Z17new_stuff_nothrowv
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// NVPTX-SAME: () #[[ATTR0:[0-9]+]] {
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// NVPTX-NEXT: entry:
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// NVPTX-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnwmRKSt9nothrow_t(i64 noundef 4, ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR4:[0-9]+]]
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// NVPTX-NEXT: ret ptr [[CALL]]
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//
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// AMDGPU-LABEL: define hidden noundef ptr @_Z17new_stuff_nothrowv
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// AMDGPU-SAME: () #[[ATTR0:[0-9]+]] {
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// AMDGPU-NEXT: entry:
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// AMDGPU-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
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// AMDGPU-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnwmRKSt9nothrow_t(i64 noundef 4, ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR4:[0-9]+]]
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// AMDGPU-NEXT: ret ptr [[CALL]]
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//
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int* new_stuff_nothrow() {
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return new (nothrow) int;
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}
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//
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// NVPTX-CXX11-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv
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// NVPTX-CXX11-SAME: () #[[ATTR0]] {
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// NVPTX-CXX11-NEXT: entry:
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// NVPTX-CXX11-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR7:[0-9]+]]
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// NVPTX-CXX11-NEXT: ret ptr [[CALL]]
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// NVPTX-CXX03-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv
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// NVPTX-CXX03-SAME: () #[[ATTR0]] {
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// NVPTX-CXX03-NEXT: entry:
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// NVPTX-CXX03-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR4]]
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// NVPTX-CXX03-NEXT: ret ptr [[CALL]]
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//
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// NVPTX-NVPTX-CXX11-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv
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// NVPTX-NVPTX-CXX11-SAME: () #[[ATTR0]] {
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// NVPTX-NVPTX-CXX11-NEXT: entry:
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// NVPTX-NVPTX-CXX11-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR7:[0-9]+]]
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// NVPTX-NVPTX-CXX11-NEXT: ret ptr [[CALL]]
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//
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// AMDGPU-CXX03-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv
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// AMDGPU-CXX03-SAME: () #[[ATTR0]] {
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// AMDGPU-CXX03-NEXT: entry:
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// AMDGPU-CXX03-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-CXX03-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
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// AMDGPU-CXX03-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR4]]
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// AMDGPU-CXX03-NEXT: ret ptr [[CALL]]
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//
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// AMDGPU-CXX11-LABEL: define hidden noundef ptr @_Z23new_array_stuff_nothrowv
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// AMDGPU-CXX11-SAME: () #[[ATTR0]] {
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// AMDGPU-CXX11-NEXT: entry:
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// AMDGPU-CXX11-NEXT: [[RETVAL:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-CXX11-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
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// AMDGPU-CXX11-NEXT: [[CALL:%.*]] = call noalias noundef ptr @_ZnamRKSt9nothrow_t(i64 noundef 136, ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR7:[0-9]+]]
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// AMDGPU-CXX11-NEXT: ret ptr [[CALL]]
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//
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int* new_array_stuff_nothrow() {
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return new (nothrow) int[34];
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}
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//
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// NVPTX-CXX11-LABEL: define hidden void @_Z20delete_stuff_nothrowPi
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// NVPTX-CXX11-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// NVPTX-CXX11-NEXT: entry:
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// NVPTX-CXX11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-CXX11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX11-NEXT: call void @_ZdlPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR8:[0-9]+]]
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// NVPTX-CXX11-NEXT: ret void
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// NVPTX-CXX03-LABEL: define hidden void @_Z20delete_stuff_nothrowPi
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// NVPTX-CXX03-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// NVPTX-CXX03-NEXT: entry:
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// NVPTX-CXX03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-CXX03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX03-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX03-NEXT: call void @_ZdlPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR6:[0-9]+]]
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// NVPTX-CXX03-NEXT: ret void
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//
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// NVPTX-NVPTX-CXX11-LABEL: define hidden void @_Z20delete_stuff_nothrowPi
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// NVPTX-NVPTX-CXX11-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// NVPTX-NVPTX-CXX11-NEXT: entry:
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// NVPTX-NVPTX-CXX11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-NVPTX-CXX11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
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// NVPTX-NVPTX-CXX11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// NVPTX-NVPTX-CXX11-NEXT: call void @_ZdlPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR8:[0-9]+]]
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// NVPTX-NVPTX-CXX11-NEXT: ret void
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//
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// AMDGPU-CXX03-LABEL: define hidden void @_Z20delete_stuff_nothrowPi
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// AMDGPU-CXX03-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// AMDGPU-CXX03-NEXT: entry:
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// AMDGPU-CXX03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-CXX03-NEXT: [[PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[PTR_ADDR]] to ptr
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// AMDGPU-CXX03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX03-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX03-NEXT: call void @_ZdlPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR6:[0-9]+]]
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// AMDGPU-CXX03-NEXT: ret void
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//
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// AMDGPU-CXX11-LABEL: define hidden void @_Z20delete_stuff_nothrowPi
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// AMDGPU-CXX11-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// AMDGPU-CXX11-NEXT: entry:
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// AMDGPU-CXX11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-CXX11-NEXT: [[PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[PTR_ADDR]] to ptr
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// AMDGPU-CXX11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX11-NEXT: call void @_ZdlPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR8:[0-9]+]]
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// AMDGPU-CXX11-NEXT: ret void
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//
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void delete_stuff_nothrow(int* ptr) {
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operator delete(ptr, nothrow);
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}
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//
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// NVPTX-CXX11-LABEL: define hidden void @_Z26delete_array_stuff_nothrowPi
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// NVPTX-CXX11-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// NVPTX-CXX11-NEXT: entry:
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// NVPTX-CXX11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-CXX11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX11-NEXT: call void @_ZdaPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR8]]
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// NVPTX-CXX11-NEXT: ret void
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// NVPTX-CXX03-LABEL: define hidden void @_Z26delete_array_stuff_nothrowPi
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// NVPTX-CXX03-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// NVPTX-CXX03-NEXT: entry:
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// NVPTX-CXX03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-CXX03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX03-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// NVPTX-CXX03-NEXT: call void @_ZdaPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR6]]
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// NVPTX-CXX03-NEXT: ret void
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//
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// NVPTX-NVPTX-CXX11-LABEL: define hidden void @_Z26delete_array_stuff_nothrowPi
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// NVPTX-NVPTX-CXX11-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// NVPTX-NVPTX-CXX11-NEXT: entry:
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// NVPTX-NVPTX-CXX11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8
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// NVPTX-NVPTX-CXX11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR]], align 8
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// NVPTX-NVPTX-CXX11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR]], align 8
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// NVPTX-NVPTX-CXX11-NEXT: call void @_ZdaPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) @nothrow) #[[ATTR8]]
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// NVPTX-NVPTX-CXX11-NEXT: ret void
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//
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// AMDGPU-CXX03-LABEL: define hidden void @_Z26delete_array_stuff_nothrowPi
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// AMDGPU-CXX03-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// AMDGPU-CXX03-NEXT: entry:
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// AMDGPU-CXX03-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-CXX03-NEXT: [[PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[PTR_ADDR]] to ptr
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// AMDGPU-CXX03-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX03-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX03-NEXT: call void @_ZdaPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR6]]
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// AMDGPU-CXX03-NEXT: ret void
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//
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// AMDGPU-CXX11-LABEL: define hidden void @_Z26delete_array_stuff_nothrowPi
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// AMDGPU-CXX11-SAME: (ptr noundef [[PTR:%.*]]) #[[ATTR0]] {
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// AMDGPU-CXX11-NEXT: entry:
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// AMDGPU-CXX11-NEXT: [[PTR_ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
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// AMDGPU-CXX11-NEXT: [[PTR_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[PTR_ADDR]] to ptr
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// AMDGPU-CXX11-NEXT: store ptr [[PTR]], ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[PTR_ADDR_ASCAST]], align 8
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// AMDGPU-CXX11-NEXT: call void @_ZdaPvRKSt9nothrow_t(ptr noundef [[TMP0]], ptr noundef nonnull align 1 dereferenceable(1) addrspacecast (ptr addrspace(1) @nothrow to ptr)) #[[ATTR8]]
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// AMDGPU-CXX11-NEXT: ret void
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//
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void delete_array_stuff_nothrow(int* ptr) {
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operator delete[](ptr, nothrow);
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}
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#pragma omp end declare target
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