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Here we introduce three new GMIR instructions to cover a set of trap intrinsics. The idea behind it is that generic intrinsics shouldn't be used with G_INTRINSIC opcode. These new instructions can match perfectly with existing trap ISD nodes. It allows X86, AArch64, RISCV and Mips to reuse SelectionDAG patterns for selection and avoid manual selection. However AMDGPU is an exception. It selects traps during legalization regardless SelectionDAG or GlobalISel. Since there are not many places where traps are used, this change attempts to clean up all the usages of G_INTRINSIC with trap intrinsics. So, there is no stage when both G_TRAP and G_INTRINSIC_W_SIDE_EFFECTS(@llvm.trap) are allowed.
19 lines
403 B
YAML
19 lines
403 B
YAML
# RUN: not --crash llc -o - -mtriple=arm64 -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: aarch64-registered-target
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---
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name: test_ubsantrap
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0:
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; CHECK: Crash kind must be 8 bit wide
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G_UBSANTRAP 4096
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; CHECK: Crash kind must be an immediate
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%5:_(s32) = IMPLICIT_DEF
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G_UBSANTRAP %5
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...
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