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16a385ba21
We already created a versioned `__tgt_kernel_arguments` struct but it
was only briefly used and its content was passed in isolation anyway.
This makes it hard to add more information in the future. With this
patch we fully embrace the struct as means to pass information from the
compiler to the plugin as part of a kernel launch.
The patch also extends and renames the struct, bumping the version
number to 2. Version 1 entries are auto-upgraded. This is in preparation
for "bare" kernel launches, per kernel dynamic shared memory, CUDA/HIP
lowering, etc.
The `__tgt_target_kernel_nowait` interface was deprecated as it was
unused. Once we actually implement support for something like that, we
can add an appropriate API.
Note: Only plugins with the `launch_kernel` interface are now supported.
That means that a new clang won't be able to use an old runtime.
An old clang can still use the new runtime since the libomptarget
interface did not change.
Differential Revision: https://reviews.llvm.org/D141232
8530 lines
584 KiB
C++
8530 lines
584 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
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// Test host codegen.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// Test host codegen.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
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// RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// We have 8 target regions, but only 7 that actually will generate offloading
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// code, only 6 will have mapped arguments, and only 4 have all-constant map
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// sizes.
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// Check target registration is registered as a Ctor.
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template<typename tx, typename ty>
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struct TT{
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tx X;
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ty Y;
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};
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long long get_val() { return 0; }
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int foo(int n) {
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int a = 0;
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short aa = 0;
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float b[10];
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float bn[n];
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double c[5][10];
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double cn[5][n];
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TT<long long, char> d;
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#pragma omp target parallel for
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for (int i = 3; i < 32; i += 5) {
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#pragma omp cancel for
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#pragma omp cancellation point for
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}
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long long k = get_val();
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#pragma omp target parallel for if(target: 0) linear(k : 3) schedule(dynamic)
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for (int i = 10; i > 1; i--) {
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a += 1;
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}
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// CHECK-32: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 0
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// CHECK-32: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPSIZEGEP]], ptr align 8 [[SIZET2]], i64 24, i1 false)
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// CHECK-32: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 1
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// CHECK-32: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPGEP]], ptr align 8 [[BPGEP]], i64 24, i1 false)
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// CHECK-32: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 2
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// CHECK-32: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPGEP]], ptr align 8 [[BCAST]], i64 24, i1 false)
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// CHECK-64: [[FPBPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 0
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// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPBPGEP]], ptr align 8 [[BPGEP]], i64 24, i1 false)
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// CHECK-64: [[FPPGEP:%.+]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 1
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// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPPGEP]], ptr align 8 [[BCAST]], i64 24, i1 false)
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// CHECK-64: [[FPSIZEGEP]] = getelementptr inbounds [[KMP_PRIVATES_T]], ptr [[KMP_PRIVATES]], i32 0, i32 2
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// CHECK-64: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[FPSIZEGEP]], ptr align 8 [[SIZET2]], i64 24, i1 false)
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int lin = 12;
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#pragma omp target parallel for if(target: 1) linear(lin, a : get_val()) nowait
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for (unsigned long long it = 2000; it >= 600; it-=400) {
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aa += 1;
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}
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#pragma omp target parallel for if(target: n>10)
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for (short it = 6; it <= 20; it-=-4) {
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a += 1;
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aa += 1;
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}
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// We capture 3 VLA sizes in this target region
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// The names below are not necessarily consistent with the names used for the
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// addresses above as some are repeated.
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#pragma omp target parallel for if(target: n>20) schedule(static, a)
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for (unsigned char it = 'z'; it >= 'a'; it+=-1) {
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a += 1;
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b[2] += 1.0;
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bn[3] += 1.0;
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c[1][2] += 1.0;
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cn[1][3] += 1.0;
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d.X += 1;
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d.Y += 1;
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}
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return a;
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}
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// Check that the offloading functions are emitted and that the arguments are
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// correct and loaded correctly for the target regions in foo().
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// Create stack storage and store argument in there.
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// Create stack storage and store argument in there.
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// Create stack storage and store argument in there.
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// Create local storage for each capture.
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// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
|
|
short aa = 0;
|
|
tx b[10];
|
|
|
|
#pragma omp target parallel for if(target: n>40)
|
|
for (long long i = -10; i < 10; i += 3) {
|
|
a += 1;
|
|
aa += 1;
|
|
b[2] += 1;
|
|
}
|
|
|
|
return a;
|
|
}
|
|
|
|
static
|
|
int fstatic(int n) {
|
|
int a = 0;
|
|
short aa = 0;
|
|
char aaa = 0;
|
|
int b[10];
|
|
|
|
#pragma omp target parallel for if(target: n>50)
|
|
for (unsigned i=100; i<10; i+=10) {
|
|
a += 1;
|
|
aa += 1;
|
|
aaa += 1;
|
|
b[2] += 1;
|
|
}
|
|
|
|
return a;
|
|
}
|
|
|
|
struct S1 {
|
|
double a;
|
|
|
|
int r1(int n){
|
|
int b = n+1;
|
|
short int c[2][n];
|
|
|
|
#pragma omp target parallel for if(target: n>60)
|
|
for (unsigned long long it = 2000; it >= 600; it -= 400) {
|
|
this->a = (double)b + 1.5;
|
|
c[1][1] = ++a;
|
|
}
|
|
|
|
return c[1][1] + (int)b;
|
|
}
|
|
};
|
|
|
|
int bar(int n){
|
|
int a = 0;
|
|
|
|
a += foo(n);
|
|
|
|
S1 S;
|
|
a += S.r1(n);
|
|
|
|
a += fstatic(n);
|
|
|
|
a += ftemplate<int>(n);
|
|
|
|
return a;
|
|
}
|
|
|
|
|
|
|
|
// We capture 2 VLA sizes in this target region
|
|
|
|
|
|
// The names below are not necessarily consistent with the names used for the
|
|
// addresses above as some are repeated.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Check that the offloading functions are emitted and that the arguments are
|
|
// correct and loaded correctly for the target regions of the callees of bar().
|
|
|
|
// Create local storage for each capture.
|
|
// Store captures in the context.
|
|
|
|
|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
|
|
// Create local storage for each capture.
|
|
// Store captures in the context.
|
|
|
|
|
|
|
|
|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
// Create local storage for each capture.
|
|
// Store captures in the context.
|
|
|
|
|
|
|
|
// To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
|
|
|
|
|
|
#endif
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
|
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP7]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP8]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP19]], align 4
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK1-NEXT: store i64 [[CALL]], ptr [[K]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP22]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load i64, ptr [[K]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP24]], ptr [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: store i32 12, ptr [[LIN]], align 4
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP26]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP28]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP30]], ptr [[A_CASTED2]], align 4
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i64, ptr [[A_CASTED2]], align 8
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP27]], ptr [[TMP32]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP27]], ptr [[TMP33]], align 8
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP34]], align 8
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP29]], ptr [[TMP35]], align 8
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP29]], ptr [[TMP36]], align 8
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP37]], align 8
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP38]], align 8
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 [[TMP31]], ptr [[TMP39]], align 8
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP40]], align 8
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP44]], ptr [[TMP43]], align 4
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP46]], ptr [[TMP45]], align 4
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP48:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP48]], ptr [[TMP47]], align 4
|
|
// CHECK1-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
|
|
// CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP49]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP50]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP52]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
|
|
// CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP49]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP53]], i32 0, i32 0
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP54]], ptr align 8 [[TMP41]], i64 24, i1 false)
|
|
// CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 1
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP55]], ptr align 8 [[TMP42]], i64 24, i1 false)
|
|
// CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 2
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP56]], ptr align 8 @.offload_sizes, i64 24, i1 false)
|
|
// CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP58]], ptr [[TMP57]], align 8
|
|
// CHECK1-NEXT: [[TMP59:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP49]])
|
|
// CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP60]], ptr [[A_CASTED3]], align 4
|
|
// CHECK1-NEXT: [[TMP61:%.*]] = load i64, ptr [[A_CASTED3]], align 8
|
|
// CHECK1-NEXT: [[TMP62:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP62]], ptr [[AA_CASTED4]], align 2
|
|
// CHECK1-NEXT: [[TMP63:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
|
|
// CHECK1-NEXT: [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP64]], 10
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP61]], ptr [[TMP65]], align 8
|
|
// CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP61]], ptr [[TMP66]], align 8
|
|
// CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP67]], align 8
|
|
// CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP63]], ptr [[TMP68]], align 8
|
|
// CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP63]], ptr [[TMP69]], align 8
|
|
// CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP70]], align 8
|
|
// CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP73]], align 4
|
|
// CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP74]], align 4
|
|
// CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP71]], ptr [[TMP75]], align 8
|
|
// CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP72]], ptr [[TMP76]], align 8
|
|
// CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.5, ptr [[TMP77]], align 8
|
|
// CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP78]], align 8
|
|
// CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP79]], align 8
|
|
// CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP80]], align 8
|
|
// CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP81]], align 8
|
|
// CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP82]], align 8
|
|
// CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP83]], align 4
|
|
// CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP84]], align 4
|
|
// CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP85]], align 4
|
|
// CHECK1-NEXT: [[TMP86:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
|
|
// CHECK1-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK1: omp_offload.failed9:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK1: omp_offload.cont10:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: [[TMP89:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP89]], ptr [[A_CASTED11]], align 4
|
|
// CHECK1-NEXT: [[TMP90:%.*]] = load i64, ptr [[A_CASTED11]], align 8
|
|
// CHECK1-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP91]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP92:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP93]], 20
|
|
// CHECK1-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
|
|
// CHECK1: omp_if.then13:
|
|
// CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK1-NEXT: [[TMP95:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK1-NEXT: [[TMP96:%.*]] = mul nuw i64 [[TMP95]], 8
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.8, i64 80, i1 false)
|
|
// CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP90]], ptr [[TMP97]], align 8
|
|
// CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP90]], ptr [[TMP98]], align 8
|
|
// CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP99]], align 8
|
|
// CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP100]], align 8
|
|
// CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP101]], align 8
|
|
// CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP102]], align 8
|
|
// CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP103]], align 8
|
|
// CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP104]], align 8
|
|
// CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP105]], align 8
|
|
// CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP106]], align 8
|
|
// CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP107]], align 8
|
|
// CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK1-NEXT: store i64 [[TMP94]], ptr [[TMP108]], align 8
|
|
// CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP109]], align 8
|
|
// CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[TMP110]], align 8
|
|
// CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[TMP111]], align 8
|
|
// CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP112]], align 8
|
|
// CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK1-NEXT: store i64 5, ptr [[TMP113]], align 8
|
|
// CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK1-NEXT: store i64 5, ptr [[TMP114]], align 8
|
|
// CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP115]], align 8
|
|
// CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP116]], align 8
|
|
// CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP117]], align 8
|
|
// CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP118]], align 8
|
|
// CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP119]], align 8
|
|
// CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr [[VLA1]], ptr [[TMP120]], align 8
|
|
// CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK1-NEXT: store i64 [[TMP96]], ptr [[TMP121]], align 8
|
|
// CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP122]], align 8
|
|
// CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[TMP123]], align 8
|
|
// CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[TMP124]], align 8
|
|
// CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP125]], align 8
|
|
// CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 [[TMP92]], ptr [[TMP126]], align 8
|
|
// CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 [[TMP92]], ptr [[TMP127]], align 8
|
|
// CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP128]], align 8
|
|
// CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP132]], align 4
|
|
// CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 10, ptr [[TMP133]], align 4
|
|
// CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 8
|
|
// CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 8
|
|
// CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 8
|
|
// CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP137]], align 8
|
|
// CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP138]], align 8
|
|
// CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP139]], align 8
|
|
// CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP140]], align 8
|
|
// CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP141]], align 8
|
|
// CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP142]], align 4
|
|
// CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
|
|
// CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP144]], align 4
|
|
// CHECK1-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
|
|
// CHECK1-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
|
|
// CHECK1: omp_offload.failed18:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT19]]
|
|
// CHECK1: omp_offload.cont19:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END21:%.*]]
|
|
// CHECK1: omp_if.else20:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END21]]
|
|
// CHECK1: omp_if.end21:
|
|
// CHECK1-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP148]])
|
|
// CHECK1-NEXT: ret i32 [[TMP147]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK1: .cancel.exit:
|
|
// CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK1: .cancel.continue:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK1: .cancel.exit2:
|
|
// CHECK1-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK1: .cancel.continue3:
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK1: cancel.cont:
|
|
// CHECK1-NEXT: ret void
|
|
// CHECK1: cancel.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..1, i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
|
|
// CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK1-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]
|
|
// CHECK1-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK1: .omp.linear.pu:
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[K1]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP14]], ptr [[K_ADDR]], align 8
|
|
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK1: .omp.linear.pu.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
|
// CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK1-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK1-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
|
|
// CHECK1-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK1-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
|
|
// CHECK1-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK1-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK1: .omp.linear.pu:
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK1: .omp.linear.pu.done:
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK1-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
|
|
// CHECK1-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP24]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK1: omp_offload.failed.i:
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !24
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = load i64, ptr [[LIN_CASTED_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !24
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias !24
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK1: .omp_outlined..3.exit:
|
|
// CHECK1-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV]], ptr [[IT]], align 2
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK1: omp.dispatch.cond:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK1: omp.dispatch.body:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK1-NEXT: store i8 [[CONV]], ptr [[IT]], align 1
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK1-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK1-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
|
|
// CHECK1-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
|
|
// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
|
|
// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
|
|
// CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
|
|
// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
|
|
// CHECK1-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
|
|
// CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8
|
|
// CHECK1-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD20]], ptr [[X]], align 8
|
|
// CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8
|
|
// CHECK1-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK1-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK1-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK1-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK1: omp.dispatch.inc:
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK1-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK1-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK1: omp.dispatch.end:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK1-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK1-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK1-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK1-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD]], ptr [[B]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK1-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.11, i64 40, i1 false)
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store ptr [[A]], ptr [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 2, ptr [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 2, ptr [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK1-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP29]], align 4
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 5, ptr [[TMP30]], align 4
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP34]], align 8
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP35]], align 8
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP36]], align 8
|
|
// CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP37]], align 8
|
|
// CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP38]], align 8
|
|
// CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
|
|
// CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
|
|
// CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP41]], align 4
|
|
// CHECK1-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
|
|
// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
|
|
// CHECK1-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
|
|
// CHECK1-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
|
|
// CHECK1-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
|
|
// CHECK1-NEXT: call void @llvm.stackrestore(ptr [[TMP47]])
|
|
// CHECK1-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i8 0, ptr [[AAA]], align 1
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
|
|
// CHECK1-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP15]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP16]], align 8
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP17]], align 8
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP21]], align 4
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 4, ptr [[TMP22]], align 4
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 8
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP27]], align 8
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP28]], align 8
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP29]], align 8
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP30]], align 8
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
|
|
// CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
|
|
// CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP33]], align 4
|
|
// CHECK1-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP36]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK1-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK1: omp_if.then:
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP7]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP10]], align 8
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP11]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[TMP12]], align 8
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP13]], align 8
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK1-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK1-NEXT: store i32 3, ptr [[TMP17]], align 4
|
|
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8
|
|
// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8
|
|
// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK1-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 8
|
|
// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK1-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 8
|
|
// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP22]], align 8
|
|
// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK1-NEXT: store ptr null, ptr [[TMP23]], align 8
|
|
// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP24]], align 8
|
|
// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK1-NEXT: store i64 0, ptr [[TMP25]], align 8
|
|
// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK1-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
|
|
// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK1-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
|
|
// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK1-NEXT: store i32 0, ptr [[TMP28]], align 4
|
|
// CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK1: omp_offload.failed:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK1: omp_offload.cont:
|
|
// CHECK1-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK1: omp_if.else:
|
|
// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK1-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK1: omp_if.end:
|
|
// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK1-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
|
// CHECK1-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..10, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: store double [[ADD]], ptr [[A]], align 8
|
|
// CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK1-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8
|
|
// CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK1-NEXT: store double [[INC]], ptr [[A4]], align 8
|
|
// CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
|
|
// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
|
|
// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
|
// CHECK1-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
|
// CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK1-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK1-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK1: cond.true:
|
|
// CHECK1-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK1: cond.false:
|
|
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: br label [[COND_END]]
|
|
// CHECK1: cond.end:
|
|
// CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK1-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK1-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK1: omp.inner.for.cond:
|
|
// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK1: omp.inner.for.body:
|
|
// CHECK1-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK1-NEXT: store i64 [[ADD]], ptr [[I]], align 8
|
|
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK1-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
|
|
// CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
|
|
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
|
|
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK1: omp.body.continue:
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK1: omp.inner.for.inc:
|
|
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK1-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK1: omp.inner.for.end:
|
|
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK1: omp.loop.exit:
|
|
// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK1-SAME: () #[[ATTR6]] {
|
|
// CHECK1-NEXT: entry:
|
|
// CHECK1-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK1-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
|
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
|
|
// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP5]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP13]], align 8
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP14]], align 8
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK3-NEXT: store i64 [[CALL]], ptr [[K]], align 8
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP20]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: store i32 12, ptr [[LIN]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP22]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP24]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP26]], ptr [[A_CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A_CASTED2]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP23]], ptr [[TMP28]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP23]], ptr [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP30]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP25]], ptr [[TMP31]], align 4
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP25]], ptr [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP33]], align 4
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP34]], align 4
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 [[TMP27]], ptr [[TMP35]], align 4
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP40]], ptr [[TMP39]], align 4
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP42]], ptr [[TMP41]], align 4
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP44]], ptr [[TMP43]], align 4
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
|
|
// CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP45]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP46]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP48:%.*]] = load ptr, ptr [[TMP47]], align 4
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP48]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
|
|
// CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP45]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP49]], i32 0, i32 0
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP50]], ptr align 4 @.offload_sizes, i32 24, i1 false)
|
|
// CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 1
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP51]], ptr align 4 [[TMP37]], i32 12, i1 false)
|
|
// CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 2
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP52]], ptr align 4 [[TMP38]], i32 12, i1 false)
|
|
// CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP54:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP54]], ptr [[TMP53]], align 4
|
|
// CHECK3-NEXT: [[TMP55:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP45]])
|
|
// CHECK3-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP56]], ptr [[A_CASTED3]], align 4
|
|
// CHECK3-NEXT: [[TMP57:%.*]] = load i32, ptr [[A_CASTED3]], align 4
|
|
// CHECK3-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP58]], ptr [[AA_CASTED4]], align 2
|
|
// CHECK3-NEXT: [[TMP59:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
|
|
// CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP60]], 10
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP57]], ptr [[TMP61]], align 4
|
|
// CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP57]], ptr [[TMP62]], align 4
|
|
// CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP63]], align 4
|
|
// CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP59]], ptr [[TMP64]], align 4
|
|
// CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP59]], ptr [[TMP65]], align 4
|
|
// CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP66]], align 4
|
|
// CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP69]], align 4
|
|
// CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP70]], align 4
|
|
// CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[TMP67]], ptr [[TMP71]], align 4
|
|
// CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[TMP68]], ptr [[TMP72]], align 4
|
|
// CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr @.offload_sizes.5, ptr [[TMP73]], align 4
|
|
// CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP74]], align 4
|
|
// CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP75]], align 4
|
|
// CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP76]], align 4
|
|
// CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP77]], align 8
|
|
// CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP78]], align 8
|
|
// CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP79]], align 4
|
|
// CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP80]], align 4
|
|
// CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP81]], align 4
|
|
// CHECK3-NEXT: [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
|
|
// CHECK3-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK3: omp_offload.failed9:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK3: omp_offload.cont10:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP84:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP84]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: [[TMP85:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP85]], ptr [[A_CASTED11]], align 4
|
|
// CHECK3-NEXT: [[TMP86:%.*]] = load i32, ptr [[A_CASTED11]], align 4
|
|
// CHECK3-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP89:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP89]], 20
|
|
// CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
|
|
// CHECK3: omp_if.then13:
|
|
// CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
|
|
// CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
|
|
// CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.8, i32 80, i1 false)
|
|
// CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP86]], ptr [[TMP95]], align 4
|
|
// CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP86]], ptr [[TMP96]], align 4
|
|
// CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP97]], align 4
|
|
// CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP98]], align 4
|
|
// CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP99]], align 4
|
|
// CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP100]], align 4
|
|
// CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP101]], align 4
|
|
// CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP102]], align 4
|
|
// CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP103]], align 4
|
|
// CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP104]], align 4
|
|
// CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP105]], align 4
|
|
// CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i64 [[TMP91]], ptr [[TMP106]], align 4
|
|
// CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP107]], align 4
|
|
// CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[TMP108]], align 4
|
|
// CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[TMP109]], align 4
|
|
// CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP110]], align 4
|
|
// CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK3-NEXT: store i32 5, ptr [[TMP111]], align 4
|
|
// CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK3-NEXT: store i32 5, ptr [[TMP112]], align 4
|
|
// CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP113]], align 4
|
|
// CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP114]], align 4
|
|
// CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP115]], align 4
|
|
// CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP116]], align 4
|
|
// CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP117]], align 4
|
|
// CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr [[VLA1]], ptr [[TMP118]], align 4
|
|
// CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK3-NEXT: store i64 [[TMP94]], ptr [[TMP119]], align 4
|
|
// CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP120]], align 4
|
|
// CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[TMP121]], align 4
|
|
// CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[TMP122]], align 4
|
|
// CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP123]], align 4
|
|
// CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i32 [[TMP88]], ptr [[TMP124]], align 4
|
|
// CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i32 [[TMP88]], ptr [[TMP125]], align 4
|
|
// CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP126]], align 4
|
|
// CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK3-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP130]], align 4
|
|
// CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 10, ptr [[TMP131]], align 4
|
|
// CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[TMP127]], ptr [[TMP132]], align 4
|
|
// CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[TMP128]], ptr [[TMP133]], align 4
|
|
// CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 4
|
|
// CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP135]], align 4
|
|
// CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP136]], align 4
|
|
// CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP137]], align 4
|
|
// CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP138]], align 8
|
|
// CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP139]], align 8
|
|
// CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP140]], align 4
|
|
// CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP141]], align 4
|
|
// CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP142]], align 4
|
|
// CHECK3-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
|
|
// CHECK3-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
|
|
// CHECK3: omp_offload.failed18:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]]
|
|
// CHECK3: omp_offload.cont19:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END21:%.*]]
|
|
// CHECK3: omp_if.else20:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END21]]
|
|
// CHECK3: omp_if.end21:
|
|
// CHECK3-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP146]])
|
|
// CHECK3-NEXT: ret i32 [[TMP145]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK3: .cancel.exit:
|
|
// CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK3: .cancel.continue:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK3: .cancel.exit2:
|
|
// CHECK3-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK3: .cancel.continue3:
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK3: cancel.cont:
|
|
// CHECK3-NEXT: ret void
|
|
// CHECK3: cancel.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..1, i32 [[TMP2]], ptr [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
|
|
// CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK3-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK3-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK3: .omp.linear.pu:
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[K1]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP15]], ptr [[TMP0]], align 8
|
|
// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK3: .omp.linear.pu.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
|
// CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..2, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK3-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
|
|
// CHECK3-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK3-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK3-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK3-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
|
|
// CHECK3-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK3-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
|
|
// CHECK3-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK3: .omp.linear.pu:
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK3: .omp.linear.pu.done:
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK3-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK3-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP24]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias !25
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias !25
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK3: omp_offload.failed.i:
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !25
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK3: .omp_outlined..3.exit:
|
|
// CHECK3-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV]], ptr [[IT]], align 2
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK3: omp.dispatch.cond:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK3: omp.dispatch.body:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK3-NEXT: store i8 [[CONV]], ptr [[IT]], align 1
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK3-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
|
|
// CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
|
|
// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
|
|
// CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
|
|
// CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
|
|
// CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
|
|
// CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4
|
|
// CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD20]], ptr [[X]], align 4
|
|
// CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4
|
|
// CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK3-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK3: omp.dispatch.inc:
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK3-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK3-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK3: omp.dispatch.end:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK3-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK3-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK3-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD]], ptr [[B]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK3-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.11, i32 40, i1 false)
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr [[A]], ptr [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK3-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP29]], align 4
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 5, ptr [[TMP30]], align 4
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP34]], align 4
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP35]], align 4
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP36]], align 4
|
|
// CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP37]], align 8
|
|
// CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP38]], align 8
|
|
// CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
|
|
// CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
|
|
// CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP41]], align 4
|
|
// CHECK3-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK3-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
|
|
// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
|
|
// CHECK3-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
|
|
// CHECK3-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
|
|
// CHECK3-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
|
|
// CHECK3-NEXT: call void @llvm.stackrestore(ptr [[TMP47]])
|
|
// CHECK3-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i8 0, ptr [[AAA]], align 1
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
|
|
// CHECK3-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP15]], align 4
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 4, ptr [[TMP22]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 4
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP27]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP28]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP29]], align 8
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP30]], align 8
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
|
|
// CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
|
|
// CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP33]], align 4
|
|
// CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP36]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK3-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK3: omp_if.then:
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP7]], align 4
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP10]], align 4
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP11]], align 4
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[TMP12]], align 4
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP13]], align 4
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK3-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK3-NEXT: store i32 3, ptr [[TMP17]], align 4
|
|
// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4
|
|
// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4
|
|
// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK3-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 4
|
|
// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK3-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 4
|
|
// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP22]], align 4
|
|
// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK3-NEXT: store ptr null, ptr [[TMP23]], align 4
|
|
// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP24]], align 8
|
|
// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK3-NEXT: store i64 0, ptr [[TMP25]], align 8
|
|
// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK3-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
|
|
// CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK3-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
|
|
// CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK3-NEXT: store i32 0, ptr [[TMP28]], align 4
|
|
// CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK3: omp_offload.failed:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK3: omp_offload.cont:
|
|
// CHECK3-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK3: omp_if.else:
|
|
// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK3-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK3: omp_if.end:
|
|
// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK3-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
|
// CHECK3-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..10, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: store double [[ADD]], ptr [[A]], align 4
|
|
// CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK3-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4
|
|
// CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK3-NEXT: store double [[INC]], ptr [[A4]], align 4
|
|
// CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
|
|
// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
|
|
// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
|
// CHECK3-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
|
// CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK3-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK3-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK3-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK3: cond.true:
|
|
// CHECK3-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK3: cond.false:
|
|
// CHECK3-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: br label [[COND_END]]
|
|
// CHECK3: cond.end:
|
|
// CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK3-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK3-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK3: omp.inner.for.cond:
|
|
// CHECK3-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK3: omp.inner.for.body:
|
|
// CHECK3-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK3-NEXT: store i64 [[ADD]], ptr [[I]], align 8
|
|
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK3-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
|
|
// CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
|
|
// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
|
|
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK3: omp.body.continue:
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK3: omp.inner.for.inc:
|
|
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK3-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK3: omp.inner.for.end:
|
|
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK3: omp.loop.exit:
|
|
// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK3-SAME: () #[[ATTR6]] {
|
|
// CHECK3-NEXT: entry:
|
|
// CHECK3-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK3-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @.omp_outlined.)
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK9: .cancel.exit:
|
|
// CHECK9-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK9: .cancel.continue:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK9: .cancel.exit2:
|
|
// CHECK9-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK9: .cancel.continue3:
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK9: cancel.cont:
|
|
// CHECK9-NEXT: ret void
|
|
// CHECK9: cancel.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
|
// CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..1, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK9-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK9-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
|
|
// CHECK9-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK9-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK9-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK9-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK9-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
|
|
// CHECK9-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
|
|
// CHECK9-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK9-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK9: .omp.linear.pu:
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK9: .omp.linear.pu.done:
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK9-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV]], ptr [[IT]], align 2
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK9: omp.dispatch.cond:
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK9-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK9: omp.dispatch.body:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK9-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK9-NEXT: store i8 [[CONV]], ptr [[IT]], align 1
|
|
// CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK9-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK9-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
|
|
// CHECK9-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
|
|
// CHECK9-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
|
|
// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
|
|
// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
|
|
// CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
|
|
// CHECK9-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK9-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
|
|
// CHECK9-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
|
|
// CHECK9-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
|
|
// CHECK9-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
|
|
// CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8
|
|
// CHECK9-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD20]], ptr [[X]], align 8
|
|
// CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
|
|
// CHECK9-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8
|
|
// CHECK9-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK9-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK9-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK9-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK9: omp.dispatch.inc:
|
|
// CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK9-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
|
|
// CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK9-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK9-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK9: omp.dispatch.end:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
|
// CHECK9-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..4, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
|
// CHECK9-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..5, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK9-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK9-NEXT: store double [[ADD]], ptr [[A]], align 8
|
|
// CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK9-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8
|
|
// CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK9-NEXT: store double [[INC]], ptr [[A4]], align 8
|
|
// CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK9-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
|
|
// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
|
|
// CHECK9-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
|
// CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK9-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK9-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK9-NEXT: entry:
|
|
// CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK9-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK9-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK9-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK9-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK9-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK9-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK9-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK9: cond.true:
|
|
// CHECK9-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK9: cond.false:
|
|
// CHECK9-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: br label [[COND_END]]
|
|
// CHECK9: cond.end:
|
|
// CHECK9-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK9-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK9-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK9: omp.inner.for.cond:
|
|
// CHECK9-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK9-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK9-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK9: omp.inner.for.body:
|
|
// CHECK9-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK9-NEXT: store i64 [[ADD]], ptr [[I]], align 8
|
|
// CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK9-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
|
|
// CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
|
|
// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
|
|
// CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK9: omp.body.continue:
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK9: omp.inner.for.inc:
|
|
// CHECK9-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK9-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK9: omp.inner.for.end:
|
|
// CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK9: omp.loop.exit:
|
|
// CHECK9-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK9-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2:[0-9]+]], i32 0, ptr @.omp_outlined.)
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK11: .cancel.exit:
|
|
// CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK11: .cancel.continue:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK11: .cancel.exit2:
|
|
// CHECK11-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK11: .cancel.continue3:
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK11: cancel.cont:
|
|
// CHECK11-NEXT: ret void
|
|
// CHECK11: cancel.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
|
// CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..1, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]]
|
|
// CHECK11-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK11-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
|
|
// CHECK11-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK11-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK11-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK11-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK11-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
|
|
// CHECK11-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
|
|
// CHECK11-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK11-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK11: .omp.linear.pu:
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK11: .omp.linear.pu.done:
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK11-SAME: () #[[ATTR3:[0-9]+]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..2, i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV]], ptr [[IT]], align 2
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..3, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK11: omp.dispatch.cond:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK11: omp.dispatch.body:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK11-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK11-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK11-NEXT: store i8 [[CONV]], ptr [[IT]], align 1
|
|
// CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK11-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK11-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
|
|
// CHECK11-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
|
|
// CHECK11-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
|
|
// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
|
|
// CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
|
|
// CHECK11-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK11-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
|
|
// CHECK11-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
|
|
// CHECK11-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
|
|
// CHECK11-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
|
|
// CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4
|
|
// CHECK11-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD20]], ptr [[X]], align 4
|
|
// CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
|
|
// CHECK11-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4
|
|
// CHECK11-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK11-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK11-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK11-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK11: omp.dispatch.inc:
|
|
// CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK11-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
|
|
// CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK11-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK11-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK11: omp.dispatch.end:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
|
// CHECK11-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..4, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
|
// CHECK11-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..5, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK11-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK11-NEXT: store double [[ADD]], ptr [[A]], align 4
|
|
// CHECK11-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK11-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4
|
|
// CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK11-NEXT: store double [[INC]], ptr [[A4]], align 4
|
|
// CHECK11-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK11-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
|
|
// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
|
|
// CHECK11-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
|
// CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK11-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..6, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
|
|
// CHECK11-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] {
|
|
// CHECK11-NEXT: entry:
|
|
// CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK11-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK11-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK11-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK11-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK11-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK11-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK11: cond.true:
|
|
// CHECK11-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK11: cond.false:
|
|
// CHECK11-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: br label [[COND_END]]
|
|
// CHECK11: cond.end:
|
|
// CHECK11-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK11-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK11-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK11: omp.inner.for.cond:
|
|
// CHECK11-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK11: omp.inner.for.body:
|
|
// CHECK11-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK11-NEXT: store i64 [[ADD]], ptr [[I]], align 8
|
|
// CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK11-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
|
|
// CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
|
|
// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
|
|
// CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK11: omp.body.continue:
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK11: omp.inner.for.inc:
|
|
// CHECK11-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK11-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK11: omp.inner.for.end:
|
|
// CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK11: omp.loop.exit:
|
|
// CHECK11-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK11-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
|
|
// CHECK17-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK17-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A_CASTED11:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
|
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[__VLA_EXPR1]], align 8
|
|
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP7]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP8]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP14]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP16]], align 8
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP17]], align 4
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP18]], align 4
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP19]], align 4
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK17-NEXT: store i64 [[CALL]], ptr [[K]], align 8
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP22]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = load i64, ptr [[K]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP24]], ptr [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP23]], i64 [[TMP25]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: store i32 12, ptr [[LIN]], align 4
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP26]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP28]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP30]], ptr [[A_CASTED2]], align 4
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i64, ptr [[A_CASTED2]], align 8
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP27]], ptr [[TMP32]], align 8
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP27]], ptr [[TMP33]], align 8
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP34]], align 8
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP29]], ptr [[TMP35]], align 8
|
|
// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP29]], ptr [[TMP36]], align 8
|
|
// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP37]], align 8
|
|
// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 [[TMP31]], ptr [[TMP38]], align 8
|
|
// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 [[TMP31]], ptr [[TMP39]], align 8
|
|
// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP40]], align 8
|
|
// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP44:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP44]], ptr [[TMP43]], align 4
|
|
// CHECK17-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP46:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP46]], ptr [[TMP45]], align 4
|
|
// CHECK17-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP48:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP48]], ptr [[TMP47]], align 4
|
|
// CHECK17-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i64 120, i64 12, ptr @.omp_task_entry., i64 -1)
|
|
// CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP49]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP50]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP52:%.*]] = load ptr, ptr [[TMP51]], align 8
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP52]], ptr align 4 [[AGG_CAPTURED]], i64 12, i1 false)
|
|
// CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP49]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP53]], i32 0, i32 0
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP54]], ptr align 8 [[TMP41]], i64 24, i1 false)
|
|
// CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 1
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP55]], ptr align 8 [[TMP42]], i64 24, i1 false)
|
|
// CHECK17-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 2
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP56]], ptr align 8 @.offload_sizes, i64 24, i1 false)
|
|
// CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP53]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP58]], ptr [[TMP57]], align 8
|
|
// CHECK17-NEXT: [[TMP59:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP49]])
|
|
// CHECK17-NEXT: [[TMP60:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP60]], ptr [[A_CASTED3]], align 4
|
|
// CHECK17-NEXT: [[TMP61:%.*]] = load i64, ptr [[A_CASTED3]], align 8
|
|
// CHECK17-NEXT: [[TMP62:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP62]], ptr [[AA_CASTED4]], align 2
|
|
// CHECK17-NEXT: [[TMP63:%.*]] = load i64, ptr [[AA_CASTED4]], align 8
|
|
// CHECK17-NEXT: [[TMP64:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP64]], 10
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP61]], ptr [[TMP65]], align 8
|
|
// CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP61]], ptr [[TMP66]], align 8
|
|
// CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 0
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP67]], align 8
|
|
// CHECK17-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP63]], ptr [[TMP68]], align 8
|
|
// CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP63]], ptr [[TMP69]], align 8
|
|
// CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i64 0, i64 1
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP70]], align 8
|
|
// CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP73]], align 4
|
|
// CHECK17-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP74]], align 4
|
|
// CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[TMP71]], ptr [[TMP75]], align 8
|
|
// CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[TMP72]], ptr [[TMP76]], align 8
|
|
// CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr @.offload_sizes.5, ptr [[TMP77]], align 8
|
|
// CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP78]], align 8
|
|
// CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP79]], align 8
|
|
// CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP80]], align 8
|
|
// CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP81]], align 8
|
|
// CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP82]], align 8
|
|
// CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP83]], align 4
|
|
// CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP84]], align 4
|
|
// CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP85]], align 4
|
|
// CHECK17-NEXT: [[TMP86:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
|
|
// CHECK17-NEXT: [[TMP87:%.*]] = icmp ne i32 [[TMP86]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP87]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK17: omp_offload.failed9:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK17: omp_offload.cont10:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i64 [[TMP61]], i64 [[TMP63]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP88:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP88]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: [[TMP89:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP89]], ptr [[A_CASTED11]], align 4
|
|
// CHECK17-NEXT: [[TMP90:%.*]] = load i64, ptr [[A_CASTED11]], align 8
|
|
// CHECK17-NEXT: [[TMP91:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP91]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP92:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP93:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP93]], 20
|
|
// CHECK17-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
|
|
// CHECK17: omp_if.then13:
|
|
// CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP2]], 4
|
|
// CHECK17-NEXT: [[TMP95:%.*]] = mul nuw i64 5, [[TMP5]]
|
|
// CHECK17-NEXT: [[TMP96:%.*]] = mul nuw i64 [[TMP95]], 8
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.8, i64 80, i1 false)
|
|
// CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP90]], ptr [[TMP97]], align 8
|
|
// CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP90]], ptr [[TMP98]], align 8
|
|
// CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP99]], align 8
|
|
// CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[TMP100]], align 8
|
|
// CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[TMP101]], align 8
|
|
// CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP102]], align 8
|
|
// CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP103]], align 8
|
|
// CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP104]], align 8
|
|
// CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 2
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP105]], align 8
|
|
// CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP106]], align 8
|
|
// CHECK17-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP107]], align 8
|
|
// CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK17-NEXT: store i64 [[TMP94]], ptr [[TMP108]], align 8
|
|
// CHECK17-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 3
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP109]], align 8
|
|
// CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[C]], ptr [[TMP110]], align 8
|
|
// CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[C]], ptr [[TMP111]], align 8
|
|
// CHECK17-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 4
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP112]], align 8
|
|
// CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK17-NEXT: store i64 5, ptr [[TMP113]], align 8
|
|
// CHECK17-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK17-NEXT: store i64 5, ptr [[TMP114]], align 8
|
|
// CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 5
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP115]], align 8
|
|
// CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP116]], align 8
|
|
// CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP117]], align 8
|
|
// CHECK17-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP118]], align 8
|
|
// CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr [[VLA1]], ptr [[TMP119]], align 8
|
|
// CHECK17-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr [[VLA1]], ptr [[TMP120]], align 8
|
|
// CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK17-NEXT: store i64 [[TMP96]], ptr [[TMP121]], align 8
|
|
// CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP122]], align 8
|
|
// CHECK17-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK17-NEXT: store ptr [[D]], ptr [[TMP123]], align 8
|
|
// CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK17-NEXT: store ptr [[D]], ptr [[TMP124]], align 8
|
|
// CHECK17-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 8
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP125]], align 8
|
|
// CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 [[TMP92]], ptr [[TMP126]], align 8
|
|
// CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 [[TMP92]], ptr [[TMP127]], align 8
|
|
// CHECK17-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 9
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP128]], align 8
|
|
// CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP130:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP132]], align 4
|
|
// CHECK17-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 10, ptr [[TMP133]], align 4
|
|
// CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 8
|
|
// CHECK17-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[TMP130]], ptr [[TMP135]], align 8
|
|
// CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[TMP131]], ptr [[TMP136]], align 8
|
|
// CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP137]], align 8
|
|
// CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP138]], align 8
|
|
// CHECK17-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP139]], align 8
|
|
// CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP140]], align 8
|
|
// CHECK17-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP141]], align 8
|
|
// CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP142]], align 4
|
|
// CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP143]], align 4
|
|
// CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP144]], align 4
|
|
// CHECK17-NEXT: [[TMP145:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
|
|
// CHECK17-NEXT: [[TMP146:%.*]] = icmp ne i32 [[TMP145]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP146]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
|
|
// CHECK17: omp_offload.failed18:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT19]]
|
|
// CHECK17: omp_offload.cont19:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END21:%.*]]
|
|
// CHECK17: omp_if.else20:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i64 [[TMP90]], ptr [[B]], i64 [[TMP2]], ptr [[VLA]], ptr [[C]], i64 5, i64 [[TMP5]], ptr [[VLA1]], ptr [[D]], i64 [[TMP92]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END21]]
|
|
// CHECK17: omp_if.end21:
|
|
// CHECK17-NEXT: [[TMP147:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP148:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP148]])
|
|
// CHECK17-NEXT: ret i32 [[TMP147]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.)
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK17: .cancel.exit:
|
|
// CHECK17-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK17: .cancel.continue:
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK17: .cancel.exit2:
|
|
// CHECK17-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK17: .cancel.continue3:
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK17: cancel.cont:
|
|
// CHECK17-NEXT: ret void
|
|
// CHECK17: cancel.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[K_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..1, i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[K]], ptr [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i64, ptr [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP0]], ptr [[DOTLINEAR_START]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK17: omp.dispatch.cond:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP2]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
|
|
// CHECK17-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
|
|
// CHECK17-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK17: omp.dispatch.body:
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]]
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK17-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3
|
|
// CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV]]
|
|
// CHECK17-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]]
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK17: omp.dispatch.inc:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK17: omp.dispatch.end:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP13]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK17: .omp.linear.pu:
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[K1]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP14]], ptr [[K_ADDR]], align 8
|
|
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK17: .omp.linear.pu.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
|
// CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[LIN_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..2, i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[LIN]], ptr [[LIN_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK17-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK17-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
|
|
// CHECK17-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK17-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK17-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
|
|
// CHECK17-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK17-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
|
|
// CHECK17-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK17: .omp.linear.pu:
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK17: .omp.linear.pu.done:
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK17-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR2]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR3]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR4]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[LIN_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED_I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
|
|
// CHECK17-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]])
|
|
// CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]])
|
|
// CHECK17-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP23]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP24]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK17: omp_offload.failed.i:
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !24
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = load i64, ptr [[AA_CASTED_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = load i64, ptr [[LIN_CASTED_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !24
|
|
// CHECK17-NEXT: [[TMP37:%.*]] = load i64, ptr [[A_CASTED_I]], align 8, !noalias !24
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i64 [[TMP33]], i64 [[TMP35]], i64 [[TMP37]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK17: .omp_outlined..3.exit:
|
|
// CHECK17-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i64 [[TMP1]], i64 [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV]], ptr [[IT]], align 2
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i64 [[TMP9]], ptr [[TMP0]], i64 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i64 [[TMP11]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], ptr noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA3]], ptr [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[VLA_ADDR4]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK17: omp.dispatch.cond:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK17-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK17: omp.dispatch.body:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK17-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK17-NEXT: store i8 [[CONV]], ptr [[IT]], align 1
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK17-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK17-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 3
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
|
|
// CHECK17-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
|
|
// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1
|
|
// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
|
|
// CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]]
|
|
// CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i64 [[TMP23]]
|
|
// CHECK17-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i64 3
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
|
|
// CHECK17-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
|
|
// CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 8
|
|
// CHECK17-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD20]], ptr [[X]], align 8
|
|
// CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 8
|
|
// CHECK17-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK17-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK17-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK17-NEXT: store i8 [[CONV23]], ptr [[Y]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK17: omp.dispatch.inc:
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK17-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK17-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK17: omp.dispatch.end:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]])
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK17-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(ptr noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]])
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]])
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK17-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]])
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK17-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK17-SAME: (ptr noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
|
|
// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD]], ptr [[B]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK17-NEXT: store ptr [[TMP3]], ptr [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[__VLA_EXPR0]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP5]], ptr [[B_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
|
|
// CHECK17-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[DOTOFFLOAD_SIZES]], ptr align 8 @.offload_sizes.11, i64 40, i1 false)
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store ptr [[A]], ptr [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP6]], ptr [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP6]], ptr [[TMP14]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 2, ptr [[TMP16]], align 8
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 2, ptr [[TMP17]], align 8
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP18]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP19]], align 8
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store i64 [[TMP2]], ptr [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP21]], align 8
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK17-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 8
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP29]], align 4
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 5, ptr [[TMP30]], align 4
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 8
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 8
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 8
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP34]], align 8
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP35]], align 8
|
|
// CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP36]], align 8
|
|
// CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP37]], align 8
|
|
// CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP38]], align 8
|
|
// CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
|
|
// CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
|
|
// CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP41]], align 4
|
|
// CHECK17-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK17-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP44:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i64 [[TMP44]]
|
|
// CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
|
|
// CHECK17-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
|
|
// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
|
|
// CHECK17-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
|
|
// CHECK17-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 8
|
|
// CHECK17-NEXT: call void @llvm.stackrestore(ptr [[TMP47]])
|
|
// CHECK17-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i8 0, ptr [[AAA]], align 1
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
|
|
// CHECK17-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP7]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP8]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[TMP14]], align 8
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP15]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[TMP16]], align 8
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[TMP17]], align 8
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP18]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP21]], align 4
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 4, ptr [[TMP22]], align 4
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 8
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 8
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP27]], align 8
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP28]], align 8
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP29]], align 8
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP30]], align 8
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
|
|
// CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
|
|
// CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP33]], align 4
|
|
// CHECK17-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK17-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP36]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 8
|
|
// CHECK17-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK17: omp_if.then:
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP5]], align 8
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i64 [[TMP1]], ptr [[TMP6]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP7]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP8]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i64 [[TMP3]], ptr [[TMP9]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP10]], align 8
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[TMP11]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[TMP12]], align 8
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP13]], align 8
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK17-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK17-NEXT: store i32 3, ptr [[TMP17]], align 4
|
|
// CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK17-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 8
|
|
// CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK17-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 8
|
|
// CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK17-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 8
|
|
// CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK17-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 8
|
|
// CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP22]], align 8
|
|
// CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK17-NEXT: store ptr null, ptr [[TMP23]], align 8
|
|
// CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP24]], align 8
|
|
// CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK17-NEXT: store i64 0, ptr [[TMP25]], align 8
|
|
// CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK17-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
|
|
// CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK17-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
|
|
// CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK17-NEXT: store i32 0, ptr [[TMP28]], align 4
|
|
// CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK17: omp_offload.failed:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK17: omp_offload.cont:
|
|
// CHECK17-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK17: omp_if.else:
|
|
// CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i64 [[TMP1]], i64 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK17-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK17: omp_if.end:
|
|
// CHECK17-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK17-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
|
// CHECK17-SAME: (ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[B_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..10, ptr [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], ptr [[TMP3]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA]], ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[VLA1]], ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i64, ptr [[VLA_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[VLA_ADDR2]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK17-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: store double [[ADD]], ptr [[A]], align 8
|
|
// CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK17-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 8
|
|
// CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK17-NEXT: store double [[INC]], ptr [[A4]], align 8
|
|
// CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]]
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i64 [[TMP14]]
|
|
// CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i64 1
|
|
// CHECK17-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
|
// CHECK17-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[AAA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], ptr [[TMP0]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AAA]], ptr [[AAA_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
|
// CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i64, ptr [[A_CASTED]], align 8
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[AA_CASTED]], align 8
|
|
// CHECK17-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i64 [[TMP2]], i64 [[TMP4]], ptr [[TMP0]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK17-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK17-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 [[AA]], ptr [[AA_ADDR]], align 8
|
|
// CHECK17-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8
|
|
// CHECK17-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK17-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK17-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
|
|
// CHECK17-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK17-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK17: cond.true:
|
|
// CHECK17-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK17: cond.false:
|
|
// CHECK17-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: br label [[COND_END]]
|
|
// CHECK17: cond.end:
|
|
// CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK17-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK17-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK17: omp.inner.for.cond:
|
|
// CHECK17-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK17: omp.inner.for.body:
|
|
// CHECK17-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK17-NEXT: store i64 [[ADD]], ptr [[I]], align 8
|
|
// CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK17-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
|
|
// CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
|
|
// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2
|
|
// CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK17: omp.body.continue:
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK17: omp.inner.for.inc:
|
|
// CHECK17-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK17-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK17: omp.inner.for.end:
|
|
// CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK17: omp.loop.exit:
|
|
// CHECK17-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK17-SAME: () #[[ATTR6]] {
|
|
// CHECK17-NEXT: entry:
|
|
// CHECK17-NEXT: call void @__tgt_register_requires(i64 1)
|
|
// CHECK17-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv
|
|
// CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: ret i64 0
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4
|
|
// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8
|
|
// CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
|
|
// CHECK19-NEXT: [[K:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
|
|
// CHECK19-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB2:[0-9]+]])
|
|
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[__VLA_EXPR1]], align 4
|
|
// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP5]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP8]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP13]], align 8
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP14]], align 8
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103() #[[ATTR4:[0-9]+]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK19-NEXT: store i64 [[CALL]], ptr [[K]], align 8
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP20]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP21]], ptr [[K]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: store i32 12, ptr [[LIN]], align 4
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP22]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP24]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP26]], ptr [[A_CASTED2]], align 4
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[A_CASTED2]], align 4
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP23]], ptr [[TMP28]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP23]], ptr [[TMP29]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP30]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP25]], ptr [[TMP31]], align 4
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP25]], ptr [[TMP32]], align 4
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP33]], align 4
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 [[TMP27]], ptr [[TMP34]], align 4
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 [[TMP27]], ptr [[TMP35]], align 4
|
|
// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP36]], align 4
|
|
// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP40:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP40]], ptr [[TMP39]], align 4
|
|
// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP42:%.*]] = load i32, ptr [[LIN]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP42]], ptr [[TMP41]], align 4
|
|
// CHECK19-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[AGG_CAPTURED]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP44:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP44]], ptr [[TMP43]], align 4
|
|
// CHECK19-NEXT: [[TMP45:%.*]] = call ptr @__kmpc_omp_target_task_alloc(ptr @[[GLOB2]], i32 [[TMP0]], i32 1, i32 72, i32 12, ptr @.omp_task_entry., i64 -1)
|
|
// CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP45]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP46]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP48:%.*]] = load ptr, ptr [[TMP47]], align 4
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP48]], ptr align 4 [[AGG_CAPTURED]], i32 12, i1 false)
|
|
// CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP45]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP49]], i32 0, i32 0
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP50]], ptr align 4 @.offload_sizes, i32 24, i1 false)
|
|
// CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 1
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP51]], ptr align 4 [[TMP37]], i32 12, i1 false)
|
|
// CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 2
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[TMP52]], ptr align 4 [[TMP38]], i32 12, i1 false)
|
|
// CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP49]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP54:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP54]], ptr [[TMP53]], align 4
|
|
// CHECK19-NEXT: [[TMP55:%.*]] = call i32 @__kmpc_omp_task(ptr @[[GLOB2]], i32 [[TMP0]], ptr [[TMP45]])
|
|
// CHECK19-NEXT: [[TMP56:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP56]], ptr [[A_CASTED3]], align 4
|
|
// CHECK19-NEXT: [[TMP57:%.*]] = load i32, ptr [[A_CASTED3]], align 4
|
|
// CHECK19-NEXT: [[TMP58:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP58]], ptr [[AA_CASTED4]], align 2
|
|
// CHECK19-NEXT: [[TMP59:%.*]] = load i32, ptr [[AA_CASTED4]], align 4
|
|
// CHECK19-NEXT: [[TMP60:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP60]], 10
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP57]], ptr [[TMP61]], align 4
|
|
// CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP57]], ptr [[TMP62]], align 4
|
|
// CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP63]], align 4
|
|
// CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP59]], ptr [[TMP64]], align 4
|
|
// CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP59]], ptr [[TMP65]], align 4
|
|
// CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP66]], align 4
|
|
// CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP68:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP69]], align 4
|
|
// CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP70]], align 4
|
|
// CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[TMP67]], ptr [[TMP71]], align 4
|
|
// CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[TMP68]], ptr [[TMP72]], align 4
|
|
// CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr @.offload_sizes.5, ptr [[TMP73]], align 4
|
|
// CHECK19-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr @.offload_maptypes.6, ptr [[TMP74]], align 4
|
|
// CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP75]], align 4
|
|
// CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP76]], align 4
|
|
// CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP77]], align 8
|
|
// CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP78]], align 8
|
|
// CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP79]], align 4
|
|
// CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP80]], align 4
|
|
// CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS8]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP81]], align 4
|
|
// CHECK19-NEXT: [[TMP82:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136.region_id, ptr [[KERNEL_ARGS8]])
|
|
// CHECK19-NEXT: [[TMP83:%.*]] = icmp ne i32 [[TMP82]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP83]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]]
|
|
// CHECK19: omp_offload.failed9:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT10]]
|
|
// CHECK19: omp_offload.cont10:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136(i32 [[TMP57]], i32 [[TMP59]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP84:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP84]], ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: [[TMP85:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP85]], ptr [[A_CASTED11]], align 4
|
|
// CHECK19-NEXT: [[TMP86:%.*]] = load i32, ptr [[A_CASTED11]], align 4
|
|
// CHECK19-NEXT: [[TMP87:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP87]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP88:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP89:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP89]], 20
|
|
// CHECK19-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]]
|
|
// CHECK19: omp_if.then13:
|
|
// CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4
|
|
// CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64
|
|
// CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]]
|
|
// CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8
|
|
// CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.8, i32 80, i1 false)
|
|
// CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP86]], ptr [[TMP95]], align 4
|
|
// CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP86]], ptr [[TMP96]], align 4
|
|
// CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP97]], align 4
|
|
// CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[TMP98]], align 4
|
|
// CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[TMP99]], align 4
|
|
// CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP100]], align 4
|
|
// CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP101]], align 4
|
|
// CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP102]], align 4
|
|
// CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP103]], align 4
|
|
// CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP104]], align 4
|
|
// CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP105]], align 4
|
|
// CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i64 [[TMP91]], ptr [[TMP106]], align 4
|
|
// CHECK19-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP107]], align 4
|
|
// CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[C]], ptr [[TMP108]], align 4
|
|
// CHECK19-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[C]], ptr [[TMP109]], align 4
|
|
// CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP110]], align 4
|
|
// CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5
|
|
// CHECK19-NEXT: store i32 5, ptr [[TMP111]], align 4
|
|
// CHECK19-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 5
|
|
// CHECK19-NEXT: store i32 5, ptr [[TMP112]], align 4
|
|
// CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP113]], align 4
|
|
// CHECK19-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP114]], align 4
|
|
// CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 6
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP115]], align 4
|
|
// CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP116]], align 4
|
|
// CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr [[VLA1]], ptr [[TMP117]], align 4
|
|
// CHECK19-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr [[VLA1]], ptr [[TMP118]], align 4
|
|
// CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 7
|
|
// CHECK19-NEXT: store i64 [[TMP94]], ptr [[TMP119]], align 4
|
|
// CHECK19-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP120]], align 4
|
|
// CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8
|
|
// CHECK19-NEXT: store ptr [[D]], ptr [[TMP121]], align 4
|
|
// CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 8
|
|
// CHECK19-NEXT: store ptr [[D]], ptr [[TMP122]], align 4
|
|
// CHECK19-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP123]], align 4
|
|
// CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i32 [[TMP88]], ptr [[TMP124]], align 4
|
|
// CHECK19-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i32 [[TMP88]], ptr [[TMP125]], align 4
|
|
// CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP126]], align 4
|
|
// CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x ptr], ptr [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8
|
|
// CHECK19-NEXT: [[TMP130:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP130]], align 4
|
|
// CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 10, ptr [[TMP131]], align 4
|
|
// CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[TMP127]], ptr [[TMP132]], align 4
|
|
// CHECK19-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[TMP128]], ptr [[TMP133]], align 4
|
|
// CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[TMP129]], ptr [[TMP134]], align 4
|
|
// CHECK19-NEXT: [[TMP135:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr @.offload_maptypes.9, ptr [[TMP135]], align 4
|
|
// CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP136]], align 4
|
|
// CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP137]], align 4
|
|
// CHECK19-NEXT: [[TMP138:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP138]], align 8
|
|
// CHECK19-NEXT: [[TMP139:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP139]], align 8
|
|
// CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP140]], align 4
|
|
// CHECK19-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP141]], align 4
|
|
// CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS17]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP142]], align 4
|
|
// CHECK19-NEXT: [[TMP143:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160.region_id, ptr [[KERNEL_ARGS17]])
|
|
// CHECK19-NEXT: [[TMP144:%.*]] = icmp ne i32 [[TMP143]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP144]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
|
|
// CHECK19: omp_offload.failed18:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT19]]
|
|
// CHECK19: omp_offload.cont19:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END21:%.*]]
|
|
// CHECK19: omp_if.else20:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160(i32 [[TMP86]], ptr [[B]], i32 [[TMP1]], ptr [[VLA]], ptr [[C]], i32 5, i32 [[TMP3]], ptr [[VLA1]], ptr [[D]], i32 [[TMP88]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END21]]
|
|
// CHECK19: omp_if.end21:
|
|
// CHECK19-NEXT: [[TMP145:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP146:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP146]])
|
|
// CHECK19-NEXT: ret i32 [[TMP145]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l103
|
|
// CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 0, ptr @.omp_outlined.)
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 5, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_cancel(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP9]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
|
|
// CHECK19: .cancel.exit:
|
|
// CHECK19-NEXT: br label [[CANCEL_EXIT:%.*]]
|
|
// CHECK19: .cancel.continue:
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_cancellationpoint(ptr @[[GLOB2]], i32 [[TMP1]], i32 2)
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP11]], label [[DOTCANCEL_EXIT2:%.*]], label [[DOTCANCEL_CONTINUE3:%.*]]
|
|
// CHECK19: .cancel.exit2:
|
|
// CHECK19-NEXT: br label [[CANCEL_EXIT]]
|
|
// CHECK19: .cancel.continue3:
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: br label [[CANCEL_CONT:%.*]]
|
|
// CHECK19: cancel.cont:
|
|
// CHECK19-NEXT: ret void
|
|
// CHECK19: cancel.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: br label [[CANCEL_CONT]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..1, i32 [[TMP2]], ptr [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[K_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[K1:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[K]], ptr [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[K_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i64, ptr [[TMP0]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP1]], ptr [[DOTLINEAR_START]], align 8
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 8, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1)
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK19: omp.dispatch.cond:
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB2]], i32 [[TMP3]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
|
|
// CHECK19-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0
|
|
// CHECK19-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK19: omp.dispatch.body:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]]
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]]
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]]
|
|
// CHECK19-NEXT: store i32 [[SUB]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]]
|
|
// CHECK19-NEXT: store i64 [[ADD]], ptr [[K1]], align 8, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD3]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP13]]
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK19: omp.dispatch.inc:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK19: omp.dispatch.end:
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK19: .omp.linear.pu:
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[K1]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP15]], ptr [[TMP0]], align 8
|
|
// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK19: .omp.linear.pu.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128
|
|
// CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP0]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[LIN_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..2, i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[LIN]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv()
|
|
// CHECK19-NEXT: store i64 [[CALL]], ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]]
|
|
// CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTLINEAR_START]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sext i32 [[TMP10]] to i64
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: [[MUL5:%.*]] = mul i64 [[TMP11]], [[TMP12]]
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV]], [[MUL5]]
|
|
// CHECK19-NEXT: [[CONV6:%.*]] = trunc i64 [[ADD]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV6]], ptr [[LIN2]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTLINEAR_START1]], align 4
|
|
// CHECK19-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTLINEAR_STEP]], align 8
|
|
// CHECK19-NEXT: [[MUL8:%.*]] = mul i64 [[TMP14]], [[TMP15]]
|
|
// CHECK19-NEXT: [[ADD9:%.*]] = add i64 [[CONV7]], [[MUL8]]
|
|
// CHECK19-NEXT: [[CONV10:%.*]] = trunc i64 [[ADD9]] to i32
|
|
// CHECK19-NEXT: store i32 [[CONV10]], ptr [[A3]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: [[CONV11:%.*]] = sext i16 [[TMP16]] to i32
|
|
// CHECK19-NEXT: [[ADD12:%.*]] = add nsw i32 [[CONV11]], 1
|
|
// CHECK19-NEXT: [[CONV13:%.*]] = trunc i32 [[ADD12]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV13]], ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[ADD14:%.*]] = add i64 [[TMP17]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD14]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]]
|
|
// CHECK19: .omp.linear.pu:
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[LIN2]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP20]], ptr [[LIN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = load i32, ptr [[A3]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP21]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]]
|
|
// CHECK19: .omp.linear.pu.done:
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map.
|
|
// CHECK19-SAME: (ptr noalias noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]], ptr noalias noundef [[TMP2:%.*]], ptr noalias noundef [[TMP3:%.*]], ptr noalias noundef [[TMP4:%.*]]) #[[ATTR6:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP2]], ptr [[DOTADDR2]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP3]], ptr [[DOTADDR3]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP4]], ptr [[DOTADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], ptr [[TMP5]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTADDR4]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP6]], ptr [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTADDR2]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP8]], ptr [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTADDR3]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP10]], ptr [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], ptr [[TMP5]], i32 0, i32 3
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP12]], ptr [[TMP13]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
|
|
// CHECK19-SAME: (i32 noundef [[TMP0:%.*]], ptr noalias noundef [[TMP1:%.*]]) #[[ATTR7:[0-9]+]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[LIN_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED_I:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[TMP1]], ptr [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTADDR1]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], ptr [[TMP3]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], ptr [[TMP4]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], ptr [[TMP4]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]])
|
|
// CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]])
|
|
// CHECK19-NEXT: store i32 [[TMP2]], ptr [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store ptr [[TMP5]], ptr [[DOTPART_ID__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store ptr [[TMP8]], ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store ptr @.omp_task_privates_map., ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store ptr [[TMP3]], ptr [[DOTTASK_T__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: store ptr [[TMP7]], ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: call void [[TMP10]](ptr [[TMP11]], ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load ptr, ptr [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], ptr [[TMP9]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON]], ptr [[TMP9]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 2, ptr [[KERNEL_ARGS_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 3, ptr [[TMP18]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[TMP13]], ptr [[TMP19]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[TMP14]], ptr [[TMP20]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[TMP15]], ptr [[TMP21]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr @.offload_maptypes, ptr [[TMP22]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP23]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP24]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP25]], align 8, !noalias !25
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 1, ptr [[TMP26]], align 8, !noalias !25
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP27]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP28]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS_I]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP29]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128.region_id, ptr [[KERNEL_ARGS_I]])
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = icmp ne i32 [[TMP30]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP31]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__3_EXIT:%.*]]
|
|
// CHECK19: omp_offload.failed.i:
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = load i16, ptr [[TMP12]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP32]], ptr [[AA_CASTED_I]], align 2, !noalias !25
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = load i32, ptr [[AA_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = load i32, ptr [[TMP16]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP34]], ptr [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = load i32, ptr [[LIN_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP17]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP36]], ptr [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: [[TMP37:%.*]] = load i32, ptr [[A_CASTED_I]], align 4, !noalias !25
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l128(i32 [[TMP33]], i32 [[TMP35]], i32 [[TMP37]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[DOTOMP_OUTLINED__3_EXIT]]
|
|
// CHECK19: .omp_outlined..3.exit:
|
|
// CHECK19-NEXT: ret i32 0
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l136
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 2, ptr @.omp_outlined..4, i32 [[TMP1]], i32 [[TMP3]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 3, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]]
|
|
// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV]], ptr [[IT]], align 2
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP9]] to i32
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV5]], ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP10]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP1]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l160
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP10]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 10, ptr @.omp_outlined..7, i32 [[TMP9]], ptr [[TMP0]], i32 [[TMP1]], ptr [[TMP2]], ptr [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], ptr [[TMP6]], ptr [[TMP7]], i32 [[TMP11]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], ptr noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], ptr noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[D_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[BN]], ptr [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA3]], ptr [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: store ptr [[CN]], ptr [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[D]], ptr [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load ptr, ptr [[BN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[VLA_ADDR4]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load ptr, ptr [[CN_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load ptr, ptr [[D_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 25, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB1]], i32 [[TMP10]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]])
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
|
|
// CHECK19: omp.dispatch.cond:
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]]
|
|
// CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
|
|
// CHECK19: omp.dispatch.body:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]]
|
|
// CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]]
|
|
// CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8
|
|
// CHECK19-NEXT: store i8 [[CONV]], ptr [[IT]], align 1
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double
|
|
// CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00
|
|
// CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float
|
|
// CHECK19-NEXT: store float [[CONV9]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i32 3
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX10]], align 4
|
|
// CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double
|
|
// CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00
|
|
// CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float
|
|
// CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4
|
|
// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8
|
|
// CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]]
|
|
// CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, ptr [[TMP6]], i32 [[TMP23]]
|
|
// CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYIDX17]], i32 3
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = load double, ptr [[ARRAYIDX18]], align 8
|
|
// CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[ADD19]], ptr [[ARRAYIDX18]], align 8
|
|
// CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], ptr [[TMP7]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = load i64, ptr [[X]], align 4
|
|
// CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD20]], ptr [[X]], align 4
|
|
// CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], ptr [[TMP7]], i32 0, i32 1
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = load i8, ptr [[Y]], align 4
|
|
// CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32
|
|
// CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1
|
|
// CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8
|
|
// CHECK19-NEXT: store i8 [[CONV23]], ptr [[Y]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD24]], ptr [[DOTOMP_IV]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
|
|
// CHECK19: omp.dispatch.inc:
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]]
|
|
// CHECK19-NEXT: store i32 [[ADD25]], ptr [[DOTOMP_LB]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
|
|
// CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]]
|
|
// CHECK19-NEXT: store i32 [[ADD26]], ptr [[DOTOMP_UB]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_DISPATCH_COND]]
|
|
// CHECK19: omp.dispatch.end:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP10]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z3bari
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]])
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
|
|
// CHECK19-NEXT: store i32 [[ADD]], ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]])
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
|
|
// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]])
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
|
|
// CHECK19-NEXT: store i32 [[ADD4]], ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]])
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
|
|
// CHECK19-NEXT: store i32 [[ADD6]], ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP8]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
|
|
// CHECK19-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
|
|
// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD]], ptr [[B]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = call ptr @llvm.stacksave()
|
|
// CHECK19-NEXT: store ptr [[TMP2]], ptr [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[__VLA_EXPR0]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
|
|
// CHECK19-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[DOTOFFLOAD_SIZES]], ptr align 4 @.offload_sizes.11, i32 40, i1 false)
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr [[THIS1]], ptr [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr [[A]], ptr [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP21]], align 4
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP22]], align 4
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[VLA]], ptr [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 4
|
|
// CHECK19-NEXT: store i64 [[TMP9]], ptr [[TMP24]], align 4
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP25]], align 4
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i64], ptr [[DOTOFFLOAD_SIZES]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP29]], align 4
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 5, ptr [[TMP30]], align 4
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[TMP26]], ptr [[TMP31]], align 4
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[TMP27]], ptr [[TMP32]], align 4
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr [[TMP28]], ptr [[TMP33]], align 4
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr @.offload_maptypes.12, ptr [[TMP34]], align 4
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP35]], align 4
|
|
// CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP36]], align 4
|
|
// CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP37]], align 8
|
|
// CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP38]], align 8
|
|
// CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP39]], align 4
|
|
// CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP40]], align 4
|
|
// CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP41]], align 4
|
|
// CHECK19-NEXT: [[TMP42:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK19-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP43]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232(ptr [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], ptr [[VLA]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP44:%.*]] = mul nsw i32 1, [[TMP1]]
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[VLA]], i32 [[TMP44]]
|
|
// CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
|
|
// CHECK19-NEXT: [[TMP45:%.*]] = load i16, ptr [[ARRAYIDX2]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP45]] to i32
|
|
// CHECK19-NEXT: [[TMP46:%.*]] = load i32, ptr [[B]], align 4
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP46]]
|
|
// CHECK19-NEXT: [[TMP47:%.*]] = load ptr, ptr [[SAVED_STACK]], align 4
|
|
// CHECK19-NEXT: call void @llvm.stackrestore(ptr [[TMP47]])
|
|
// CHECK19-NEXT: ret i32 [[ADD3]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x ptr], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i8 0, ptr [[AAA]], align 1
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i8, ptr [[AAA]], align 1
|
|
// CHECK19-NEXT: store i8 [[TMP4]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP8]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP13]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store i32 [[TMP5]], ptr [[TMP14]], align 4
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP15]], align 4
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP21]], align 4
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 4, ptr [[TMP22]], align 4
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[TMP19]], ptr [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[TMP20]], ptr [[TMP24]], align 4
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr @.offload_sizes.14, ptr [[TMP25]], align 4
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr @.offload_maptypes.15, ptr [[TMP26]], align 4
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP27]], align 4
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP28]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP29]], align 8
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP30]], align 8
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP31]], align 4
|
|
// CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP32]], align 4
|
|
// CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP33]], align 4
|
|
// CHECK19-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK19-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP36:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP36]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
|
|
// CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2
|
|
// CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x ptr], align 4
|
|
// CHECK19-NEXT: store i32 [[N]], ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 0, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i16 0, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP0]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i16, ptr [[AA]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP2]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
|
|
// CHECK19: omp_if.then:
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP5]], align 4
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[TMP6]], align 4
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP7]], align 4
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP8]], align 4
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 [[TMP3]], ptr [[TMP9]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP10]], align 4
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[TMP11]], align 4
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[TMP12]], align 4
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP13]], align 4
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8
|
|
// CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 0
|
|
// CHECK19-NEXT: store i32 2, ptr [[TMP16]], align 4
|
|
// CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 1
|
|
// CHECK19-NEXT: store i32 3, ptr [[TMP17]], align 4
|
|
// CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 2
|
|
// CHECK19-NEXT: store ptr [[TMP14]], ptr [[TMP18]], align 4
|
|
// CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 3
|
|
// CHECK19-NEXT: store ptr [[TMP15]], ptr [[TMP19]], align 4
|
|
// CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 4
|
|
// CHECK19-NEXT: store ptr @.offload_sizes.17, ptr [[TMP20]], align 4
|
|
// CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 5
|
|
// CHECK19-NEXT: store ptr @.offload_maptypes.18, ptr [[TMP21]], align 4
|
|
// CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 6
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP22]], align 4
|
|
// CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 7
|
|
// CHECK19-NEXT: store ptr null, ptr [[TMP23]], align 4
|
|
// CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 8
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP24]], align 8
|
|
// CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 9
|
|
// CHECK19-NEXT: store i64 0, ptr [[TMP25]], align 8
|
|
// CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 10
|
|
// CHECK19-NEXT: store [3 x i32] [i32 1, i32 0, i32 0], ptr [[TMP26]], align 4
|
|
// CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 11
|
|
// CHECK19-NEXT: store [3 x i32] zeroinitializer, ptr [[TMP27]], align 4
|
|
// CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], ptr [[KERNEL_ARGS]], i32 0, i32 12
|
|
// CHECK19-NEXT: store i32 0, ptr [[TMP28]], align 4
|
|
// CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(ptr @[[GLOB2]], i64 -1, i32 1, i32 0, ptr @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197.region_id, ptr [[KERNEL_ARGS]])
|
|
// CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
|
|
// CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
|
|
// CHECK19: omp_offload.failed:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]]
|
|
// CHECK19: omp_offload.cont:
|
|
// CHECK19-NEXT: br label [[OMP_IF_END:%.*]]
|
|
// CHECK19: omp_if.else:
|
|
// CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197(i32 [[TMP1]], i32 [[TMP3]], ptr [[B]]) #[[ATTR4]]
|
|
// CHECK19-NEXT: br label [[OMP_IF_END]]
|
|
// CHECK19: omp_if.end:
|
|
// CHECK19-NEXT: [[TMP31:%.*]] = load i32, ptr [[A]], align 4
|
|
// CHECK19-NEXT: ret i32 [[TMP31]]
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l232
|
|
// CHECK19-SAME: (ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP4]], ptr [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[B_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 5, ptr @.omp_outlined..10, ptr [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], ptr [[TMP3]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], ptr noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA]], ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[VLA1]], ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: store ptr [[C]], ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[THIS_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[VLA_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[VLA_ADDR2]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load ptr, ptr [[C_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 3, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8u(ptr @[[GLOB1]], i32 [[TMP5]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP8]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]]
|
|
// CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400
|
|
// CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[SUB]], ptr [[IT]], align 8
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double
|
|
// CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
|
|
// CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: store double [[ADD]], ptr [[A]], align 4
|
|
// CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP0]], i32 0, i32 0
|
|
// CHECK19-NEXT: [[TMP13:%.*]] = load double, ptr [[A4]], align 4
|
|
// CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00
|
|
// CHECK19-NEXT: store double [[INC]], ptr [[A4]], align 4
|
|
// CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16
|
|
// CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]]
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[TMP3]], i32 [[TMP14]]
|
|
// CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, ptr [[ARRAYIDX]], i32 1
|
|
// CHECK19-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX6]], align 2
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD7]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP5]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l214
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i8, ptr [[AAA_ADDR]], align 1
|
|
// CHECK19-NEXT: store i8 [[TMP5]], ptr [[AAA_CASTED]], align 1
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i32, ptr [[AAA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 4, ptr @.omp_outlined..13, i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], ptr [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AAA]], ptr [[AAA_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l197
|
|
// CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[TMP1]], ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_CASTED]], align 4
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: store i16 [[TMP3]], ptr [[AA_CASTED]], align 2
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i32, ptr [[AA_CASTED]], align 4
|
|
// CHECK19-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB2]], i32 3, ptr @.omp_outlined..16, i32 [[TMP2]], i32 [[TMP4]], ptr [[TMP0]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16
|
|
// CHECK19-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4
|
|
// CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
|
|
// CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8
|
|
// CHECK19-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: store i32 [[AA]], ptr [[AA_ADDR]], align 4
|
|
// CHECK19-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4
|
|
// CHECK19-NEXT: store i64 0, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 6, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8
|
|
// CHECK19-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
|
|
// CHECK19-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB1]], i32 [[TMP2]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
|
|
// CHECK19-NEXT: [[TMP3:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6
|
|
// CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
|
|
// CHECK19: cond.true:
|
|
// CHECK19-NEXT: br label [[COND_END:%.*]]
|
|
// CHECK19: cond.false:
|
|
// CHECK19-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: br label [[COND_END]]
|
|
// CHECK19: cond.end:
|
|
// CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
|
|
// CHECK19-NEXT: store i64 [[COND]], ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
|
|
// CHECK19-NEXT: store i64 [[TMP5]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
|
|
// CHECK19: omp.inner.for.cond:
|
|
// CHECK19-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTOMP_UB]], align 8
|
|
// CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]]
|
|
// CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
|
|
// CHECK19: omp.inner.for.body:
|
|
// CHECK19-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3
|
|
// CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]]
|
|
// CHECK19-NEXT: store i64 [[ADD]], ptr [[I]], align 8
|
|
// CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD2]], ptr [[A_ADDR]], align 4
|
|
// CHECK19-NEXT: [[TMP10:%.*]] = load i16, ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP10]] to i32
|
|
// CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1
|
|
// CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
|
|
// CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2
|
|
// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2
|
|
// CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1
|
|
// CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4
|
|
// CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
|
|
// CHECK19: omp.body.continue:
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
|
|
// CHECK19: omp.inner.for.inc:
|
|
// CHECK19-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: [[ADD6:%.*]] = add nsw i64 [[TMP12]], 1
|
|
// CHECK19-NEXT: store i64 [[ADD6]], ptr [[DOTOMP_IV]], align 8
|
|
// CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]]
|
|
// CHECK19: omp.inner.for.end:
|
|
// CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
|
|
// CHECK19: omp.loop.exit:
|
|
// CHECK19-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB1]], i32 [[TMP2]])
|
|
// CHECK19-NEXT: ret void
|
|
//
|
|
//
|
|
// CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
|
|
// CHECK19-SAME: () #[[ATTR6]] {
|
|
// CHECK19-NEXT: entry:
|
|
// CHECK19-NEXT: call void @__tgt_register_requires(i64 1)
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// CHECK19-NEXT: ret void
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//
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