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As the LoongArch port is largely modeled after RISCV it has the same behavior of not accepting `generic` as a CPU name. For better compatibility with consumers of LLVM (e.g. mesa) follow D121149's suit and treat `generic` the same as an empty CPU name. Differential Revision: https://reviews.llvm.org/D134412
30 lines
1023 B
LLVM
30 lines
1023 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc --mtriple=loongarch32 --mcpu=generic < %s \
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; RUN: | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch32 --mcpu=generic-la32 < %s \
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; RUN: | FileCheck %s --check-prefix=LA32
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; RUN: llc --mtriple=loongarch64 --mcpu=generic < %s \
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; RUN: | FileCheck %s --check-prefix=LA64
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; RUN: llc --mtriple=loongarch64 --mcpu=generic-la64 < %s \
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; RUN: | FileCheck %s --check-prefix=LA64
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;; The CPU name "generic" should map to the corresponding concrete names
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;; according to the target triple's bitness.
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define i64 @f(i64 signext %a, i64 signext %b) {
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; LA32-LABEL: f:
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; LA32: # %bb.0:
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; LA32-NEXT: add.w $a1, $a1, $a3
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; LA32-NEXT: add.w $a2, $a0, $a2
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; LA32-NEXT: sltu $a0, $a2, $a0
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; LA32-NEXT: add.w $a1, $a1, $a0
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; LA32-NEXT: move $a0, $a2
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; LA32-NEXT: ret
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;
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; LA64-LABEL: f:
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; LA64: # %bb.0:
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; LA64-NEXT: add.d $a0, $a0, $a1
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; LA64-NEXT: ret
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%1 = add nsw i64 %a, %b
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ret i64 %1
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}
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