llvm-project

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History

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504 )

The Qualcomm uC Xqcics extension adds 8 conditional select instructions.

The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest

This patch adds assembler only support.

---------

Co-authored-by: Harsh Chandel <hchandel@qti.qualcomm.com>

2024-12-12 11:12:09 +05:30

AsmParser

[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113 )

2024-12-01 17:06:22 +05:30

Disassembler

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504 )

2024-12-12 11:12:09 +05:30

GISel

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427 )

2024-12-10 22:17:52 -08:00

MCA

…

MCTargetDesc

[RISCV] Add Qualcomm uC Xqcia (Arithmetic) extension (#118113 )

2024-12-01 17:06:22 +05:30

TargetInfo

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CMakeLists.txt

[RISCV] Set a barrier between mask producer and user of V0 (#114012 )

2024-11-29 13:25:53 +08:00

RISCV.h

[RISCV] Introduce VLOptimizer pass (#108640 )

2024-10-11 09:45:35 -04:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVAsmPrinter.cpp

[XRay][RISCV] RISCV support for XRay (#117368 )

2024-12-10 17:57:04 -08:00

RISCVCallingConv.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVCallingConv.h

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RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVCombine.td

[RISCV] Remove constant_fold_cast_op from RISCVPostLegalizerCombiner.

2024-11-12 23:28:48 -08:00

RISCVConstantPoolValue.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVConstantPoolValue.h

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RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778 )

2024-12-06 15:16:07 +05:30

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Teach expandRV32ZdinxStore to handle memoperand not being present. (#113981 )

2024-10-28 22:37:47 -07:00

RISCVFeatures.td

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504 )

2024-12-12 11:12:09 +05:30

RISCVFrameLowering.cpp

[RISCV] Rename a lambda to have plural nouns to reflect that it contains a loop. NFC

2024-12-11 11:44:36 -08:00

RISCVFrameLowering.h

[RISCV] Add stack clash protection (#117612 )

2024-12-10 16:48:26 +00:00

RISCVGatherScatterLowering.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVGISel.td

[RISCV] Add i16->i32 G_ZEXT/G_SEXT patterns for RV64.

2024-12-06 21:49:35 -08:00

RISCVIndirectBranchTracking.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVInsertReadWriteCSR.cpp

…

RISCVInsertVSETVLI.cpp

[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778 )

2024-12-06 15:16:07 +05:30

RISCVInsertWriteVXRM.cpp

[RISCV] Allow hoisting VXRM writes out of loops speculatively (#110044 )

2024-11-27 13:31:39 -08:00

RISCVInstrFormats.td

[RISCV][MC] Support Assembling 48- and 64-bit Instructions (#110022 )

2024-10-08 14:09:07 +01:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

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RISCVInstrGISel.td

[RISCV][GISel] Custom promote s32 G_SHL/ASHR/LSHR on RV64. (#115559 )

2024-11-11 20:59:21 -08:00

RISCVInstrInfo.cpp

[RISCV] Use OperandType from MCInstrDesc in RISCVInstrInfo::createMIROperandComment. NFCI (#119637 )

2024-12-11 21:12:46 -08:00

RISCVInstrInfo.h

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889 )

2024-11-25 18:59:31 -08:00

RISCVInstrInfo.td

[RISCV][GISel] Port TrailingOnesMask PatLeaf. (#119427 )

2024-12-10 22:17:52 -08:00

RISCVInstrInfoA.td

[RISCV] Make A implies Zaamo and Zalrsc (#116907 )

2024-11-22 10:35:38 +08:00

RISCVInstrInfoC.td

[RISCV] Only allow 5 bit shift amounts in disassembler for RV32. (#115432 )

2024-11-08 09:12:25 -08:00

RISCVInstrInfoD.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoF.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoM.td

…

RISCVInstrInfoSFB.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163 )

2024-10-29 21:23:31 -07:00

RISCVInstrInfoV.td

[RISCV] Mark vmvNr.v as implicitly using vtype (#118414 )

2024-12-04 15:10:57 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Use getSignedTargetConstant. NFC

2024-11-18 12:20:44 -08:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Fix some isel patterns that used a type where we normally put a regclass. NFC

2024-11-08 18:11:39 -08:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match (#118391 )

2024-12-02 13:39:12 -08:00

RISCVInstrInfoXCV.td

[RISCV] Add OperandType for condition code arguments used by select and SFB pseudos. (#114163 )

2024-10-29 21:23:31 -07:00

RISCVInstrInfoXqci.td

[RISCV] Add Qualcomm uC Xqcics(Conditional Select) extension (#119504 )

2024-12-12 11:12:09 +05:30

RISCVInstrInfoXSf.td

[RISCV] Add hasPostISelHook to sf.vfnrclip pseudo instructions. (#114274 )

2024-10-30 11:52:49 -07:00

RISCVInstrInfoXTHead.td

[RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.

2024-11-19 21:41:14 -08:00

RISCVInstrInfoXVentana.td

…

RISCVInstrInfoXwch.td

…

RISCVInstrInfoZa.td

…

RISCVInstrInfoZalasr.td

…

RISCVInstrInfoZb.td

[RISCV][GISEl] Simplify GISelPredicateCode for binop_with_non_imm12. NFC

2024-12-10 09:44:25 -08:00

RISCVInstrInfoZc.td

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446 )

2024-09-26 22:56:12 -07:00

RISCVInstrInfoZcmop.td

…

RISCVInstrInfoZfa.td

[RISCV] f32 roundeven pattern missed for Zfa (#118672 )

2024-12-04 13:52:20 -08:00

RISCVInstrInfoZfbfmin.td

…

RISCVInstrInfoZfh.td

[RISCV][GISel] Add register class to some isel output patterns so they can be imported.

2024-11-24 19:29:52 -08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

…

RISCVInstrInfoZicond.td

…

RISCVInstrInfoZimop.td

…

RISCVInstrInfoZk.td

[RISCV] Combine RVBUnary and RVKUnary into classes that are more similar to ALU(W)_r(r/i). NFC (#111279 )

2024-10-06 11:47:30 -07:00

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317 )

2024-10-31 10:21:14 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Merge GPRPair and GPRF64Pair (#116094 )

2024-11-20 10:08:55 +00:00

RISCVISelDAGToDAG.h

…

RISCVISelLowering.cpp

[RISCV] Merge shuffle sources if lanes are disjoint (#119401 )

2024-12-12 13:41:27 +08:00

RISCVISelLowering.h

[RISCV] Add stack clash protection (#117612 )

2024-12-10 16:48:26 +00:00

RISCVLandingPadSetup.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVMachineFunctionInfo.cpp

[RISCV] Add stack clash protection (#117612 )

2024-12-10 16:48:26 +00:00

RISCVMachineFunctionInfo.h

[RISCV] Add stack clash protection (#117612 )

2024-12-10 16:48:26 +00:00

RISCVMacroFusion.td

…

RISCVMakeCompressible.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVMergeBaseOffset.cpp

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336 )

2024-10-01 22:09:27 -07:00

RISCVMoveMerger.cpp

…

RISCVOptWInstrs.cpp

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RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.

2024-12-05 16:43:30 -08:00

RISCVProcessors.td

[RISCV] Add tune info for mem* expansion (#118439 )

2024-12-06 14:48:37 +08:00

RISCVProfiles.td

[RISCV] Use the 'B' extension in RISC-V profile definitions (#113942 )

2024-11-10 07:18:05 +00:00

RISCVPushPopOptimizer.cpp

…

RISCVRedundantCopyElimination.cpp

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RISCVRegisterInfo.cpp

[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756 )

2024-12-06 14:07:27 -05:00

RISCVRegisterInfo.h

[RISCV] Correct the precedence in isVRegClass (#116579 )

2024-11-18 18:12:57 +08:00

RISCVRegisterInfo.td

[RISCV] Merge GPRPair and GPRF64Pair (#116094 )

2024-11-20 10:08:55 +00:00

RISCVSchedRocket.td

…

RISCVSchedSiFive7.td

[llvm][NFC] Fix typos: replace “avaliable” with “available” across various files (#114524 )

2024-11-01 13:25:04 +00:00

RISCVSchedSiFiveP400.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893 )

2024-11-21 10:59:46 -08:00

RISCVSchedSiFiveP600.td

[RISCV] Fix the worst case for VSHA2MS in SiFive P400/P600 scheduling models (#116893 )

2024-11-21 10:59:46 -08:00

RISCVSchedSyntacoreSCR1.td

…

RISCVSchedSyntacoreSCR7.td

[RISCV] Add scheduling model for Syntacore SCR7 (#108814 )

2024-09-17 18:52:55 +03:00

RISCVSchedSyntacoreSCR345.td

…

RISCVSchedule.td

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RISCVScheduleV.td

[RISCV] Assign different scheduling classes for VMADC/VMSBC (#113009 )

2024-10-28 09:37:54 -07:00

RISCVScheduleXSf.td

…

RISCVScheduleZb.td

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RISCVScheduleZvk.td

[RISCV] Assign separate PseudoVSHA2MS_VV opcodes for each SEW (#114317 )

2024-10-31 10:21:14 -07:00

RISCVSchedXiangShanNanHu.td

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RISCVSubtarget.cpp

[RISCV] Add TuneDisableLatencySchedHeuristic

2024-11-28 15:16:23 +08:00

RISCVSubtarget.h

[XRay][RISCV] RISCV support for XRay (#117368 )

2024-12-10 17:57:04 -08:00

RISCVSystemOperands.td

…

RISCVTargetMachine.cpp

[RISCV] Enable merging of external globals by default (#117880 )

2024-12-11 16:06:49 +00:00

RISCVTargetMachine.h

[RISCV] Set a barrier between mask producer and user of V0 (#114012 )

2024-11-29 13:25:53 +08:00

RISCVTargetObjectFile.cpp

…

RISCVTargetObjectFile.h

…

RISCVTargetTransformInfo.cpp

[RISCV][TTI] Model the cost of insert/extractelt when the vector split into multiple register group and idx exceed single group. (#118401 )

2024-12-12 09:26:19 +08:00

RISCVTargetTransformInfo.h

[SLPVectorizer, TargetTransformInfo, SystemZ] Improve SLP getGatherCost(). (#112491 )

2024-11-29 21:19:45 +01:00

RISCVVectorMaskDAGMutation.cpp

[RISCV] Set a barrier between mask producer and user of V0 (#114012 )

2024-11-29 13:25:53 +08:00

RISCVVectorPeephole.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00

RISCVVLOptimizer.cpp

[RISCV][VLOPT] Add vector narrowing integer right shift instructions to isSupportedInstr (#119602 )

2024-12-11 13:51:19 -05:00

RISCVZacasABIFix.cpp

[RISCV] Remove unused includes (NFC) (#115814 )

2024-11-11 22:54:54 -08:00