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The altera kernel name restriction check finds kernel files and include directives whose filename is "kernel.cl", "Verilog.cl", or "VHDL.cl". Such kernel file names cause the Altera Offline Compiler to generate intermediate design files that have the same names as certain internal files, which leads to a compilation error. As per the "Guidelines for Naming the Kernel" section in the "Intel FPGA SDK for OpenCL Pro Edition: Programming Guide." This reverts the reversion from 43a38a65233039b5e71797a644d41a890f8d7f2b.
---------------------------------- Documentation in clang-tools-extra ---------------------------------- To generate documentation in HTML format from files in clang-tools-extra/docs, build the docs-clang-tools-html target. To generate documentation from the source code using Doxygen, build the doxygen-clang-tools target.