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There are two problems with _BitInt prior to this patch: 1. For at least some values of N, we cannot use LLVM's iN for the type of struct elements, array elements, allocas, global variables, and so on, because the LLVM layout for that type does not match the high-level layout of _BitInt(N). Example: Currently for i128:128 targets correct implementation is possible either for __int128 or for _BitInt(129+) with lowering to iN, but not both, since we have now correct implementation of __int128 in place after a21abc7. When this happens, opaque [M x i8] types used, where M = sizeof(_BitInt(N)). 2. LLVM doesn't guarantee any particular extension behavior for integer types that aren't a multiple of 8. For this reason, all _BitInt types are now have in-memory representation that is a whole number of bytes. I.e. for example _BitInt(17) now will have memory layout type i32. This patch also introduces concept of load/store type and adds an API to CodeGenTypes that returns the IR type that should be used for load and store operations. This is particularly useful for the case when a _BitInt ends up having array of bytes as memory layout type. For _BitInt(N), let M = sizeof(_BitInt(N)), and let BITS = M * 8. Loads and stores of iM would both (1) produce far better code from the backends and (2) be far more optimizable by IR passes than loads and stores of [M x i8]. Fixes https://github.com/llvm/llvm-project/issues/85139 Fixes https://github.com/llvm/llvm-project/issues/83419 --------- Co-authored-by: John McCall <rjmccall@gmail.com>
133 lines
5.3 KiB
C
133 lines
5.3 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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// RUN: %clang_cc1 -triple arm-unknown-unknown -O0 -std=c23 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-O0
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// RUN: %clang_cc1 -triple arm-unknown-unknown -O1 -std=c23 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-O1
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// Verify that the result from the intrinsic call is zero extended to avoid that
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// we get a negative result from popcountg/ctzg/clzg.
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_popcountg_ubi1(
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// CHECK-O0-SAME: ) #[[ATTR0:[0-9]+]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i8, align 1
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// CHECK-O0-NEXT: store i8 1, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP0]] to i1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i1 @llvm.ctpop.i1(i1 [[LOADEDV]])
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i1 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_popcountg_ubi1(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 1
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//
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int test_popcountg_ubi1() {
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unsigned _BitInt(1) a = 1uwb;
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return __builtin_popcountg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_popcountg_ubi2(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i8, align 1
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// CHECK-O0-NEXT: store i8 3, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP0]] to i2
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i2 @llvm.ctpop.i2(i2 [[LOADEDV]])
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i2 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_popcountg_ubi2(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 2
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//
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int test_popcountg_ubi2() {
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unsigned _BitInt(2) a = 3uwb;
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return __builtin_popcountg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_ctzg_ubi1(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i8, align 1
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// CHECK-O0-NEXT: store i8 0, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP0]] to i1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i1 @llvm.cttz.i1(i1 [[LOADEDV]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i1 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_ctzg_ubi1(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 1
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//
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int test_ctzg_ubi1() {
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unsigned _BitInt(1) a = 0uwb;
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return __builtin_ctzg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_ctzg_ubi2(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i8, align 1
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// CHECK-O0-NEXT: store i8 0, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP0]] to i2
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i2 @llvm.cttz.i2(i2 [[LOADEDV]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i2 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_ctzg_ubi2(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 2
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//
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int test_ctzg_ubi2() {
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unsigned _BitInt(2) a = 0uwb;
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return __builtin_ctzg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_clzg_ubi1(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i8, align 1
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// CHECK-O0-NEXT: store i8 0, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP0]] to i1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i1 @llvm.ctlz.i1(i1 [[LOADEDV]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i1 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_clzg_ubi1(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 1
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//
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int test_clzg_ubi1() {
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unsigned _BitInt(1) a = 0uwb;
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return __builtin_clzg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_clzg_ubi2(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i8, align 1
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// CHECK-O0-NEXT: store i8 0, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i8, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[LOADEDV:%.*]] = trunc i8 [[TMP0]] to i2
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i2 @llvm.ctlz.i2(i2 [[LOADEDV]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i2 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_clzg_ubi2(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 2
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//
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int test_clzg_ubi2() {
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unsigned _BitInt(2) a = 0uwb;
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return __builtin_clzg(a);
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}
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