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- Mention this change in Clang release notes Before: - Clang emits "invalid output constraint '=@cceq' in asm" https://gcc.godbolt.org/z/b9crfEo8h After: - For aarch64 targets (with __aarch64__ defined), Clang validates and parses flag output constraints to generate LLVM IR. Differential Revision: https://reviews.llvm.org/D149123
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
// RUN: %clang_cc1 -O2 -emit-llvm %s -o - -triple aarch64 | FileCheck %s
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int test_cceq(int a, int* b) {
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// CHECK-LABEL: @test_cceq
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cceq},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cceq"(*b));
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return a;
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}
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int test_ccne(int a, int* b) {
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// CHECK-LABEL: @test_ccne
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccne},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccne"(*b));
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return a;
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}
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int test_cccs(int a, int* b) {
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// CHECK-LABEL: @test_cccs
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cccs},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cccs"(*b));
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return a;
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}
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int test_cchs(int a, int* b) {
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// CHECK-LABEL: @test_cchs
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cchs},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cchs"(*b));
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return a;
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}
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int test_cccc(int a, int* b) {
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// CHECK-LABEL: @test_cccc
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cccc},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cccc"(*b));
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return a;
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}
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int test_cclo(int a, int* b) {
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// CHECK-LABEL: @test_cclo
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cclo},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cclo"(*b));
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return a;
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}
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int test_ccmi(int a, int* b) {
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// CHECK-LABEL: @test_ccmi
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccmi},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccmi"(*b));
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return a;
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}
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int test_ccpl(int a, int* b) {
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// CHECK-LABEL: @test_ccpl
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccpl},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccpl"(*b));
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return a;
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}
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int test_ccvs(int a, int* b) {
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// CHECK-LABEL: @test_ccvs
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccvs},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccvs"(*b));
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return a;
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}
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int test_ccvc(int a, int* b) {
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// CHECK-LABEL: @test_ccvc
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccvc},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccvc"(*b));
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return a;
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}
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int test_cchi(int a, int* b) {
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// CHECK-LABEL: @test_cchi
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cchi},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cchi"(*b));
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return a;
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}
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int test_ccls(int a, int* b) {
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// CHECK-LABEL: @test_ccls
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccls},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccls"(*b));
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return a;
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}
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int test_ccge(int a, int* b) {
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// CHECK-LABEL: @test_ccge
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccge},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccge"(*b));
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return a;
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}
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int test_cclt(int a, int* b) {
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// CHECK-LABEL: @test_cclt
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@cclt},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@cclt"(*b));
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return a;
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}
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int test_ccgt(int a, int* b) {
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// CHECK-LABEL: @test_ccgt
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccgt},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccgt"(*b));
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return a;
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}
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int test_ccle(int a, int* b) {
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// CHECK-LABEL: @test_ccle
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// CHECK: = tail call { i32, i32 } asm "ands ${0:w}, ${0:w}, #3", "=r,={@ccle},0"(i32 %a)
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asm("ands %w[a], %w[a], #3"
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: [a] "+r"(a), "=@ccle"(*b));
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return a;
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}
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