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[RISCV] RISCV vector calling convention (1/2)
This is the vector calling convention based on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc,
the idea is to split between "scalar" callee-saved registers
and "vector" callee-saved registers. "scalar" ones remain the
original strategy, however, "vector" ones are handled together
with RVV objects.
The stack layout would be:
|--------------------------| <-- FP
| callee-allocated save |
| area for register varargs|
|--------------------------|
| callee-saved registers | <-- scalar callee-saved
| (scalar) |
|--------------------------|
| RVV alignment padding |
|--------------------------|
| callee-saved registers | <-- vector callee-saved
| (vector) |
|--------------------------|
| RVV objects |
|--------------------------|
| padding before RVV |
|--------------------------|
| scalar local variables |
|--------------------------| <-- BP
| variable size objects |
|--------------------------| <-- SP
Note: This patch doesn't contain "tuple" type, e.g. vint32m1x2.
It will be handled in https://github.com/riscv-non-isa/riscv-elf-psabi-doc (2/2).
Differential Revision: https://reviews.llvm.org/D154576
33 lines
1.2 KiB
C++
33 lines
1.2 KiB
C++
// REQUIRES: riscv-registered-target
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// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v \
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// RUN: -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
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#include <riscv_vector.h>
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// CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @_Z3baru15__rvv_int32m1_t
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vint32m1_t __attribute__((riscv_vector_cc)) bar(vint32m1_t input);
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vint32m1_t test_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
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vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
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vint32m1_t ret = bar(input);
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__riscv_vse32_v_i32m1(base, val, vl);
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return ret;
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}
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// CHECK-LLVM: call riscv_vector_cc <vscale x 2 x i32> @_Z3baru15__rvv_int32m1_t
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[[riscv::vector_cc]] vint32m1_t bar(vint32m1_t input);
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vint32m1_t test_vector_cc_attr2(vint32m1_t input, int32_t *base, size_t vl) {
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vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
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vint32m1_t ret = bar(input);
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__riscv_vse32_v_i32m1(base, val, vl);
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return ret;
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}
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// CHECK-LLVM: call <vscale x 2 x i32> @_Z3bazu15__rvv_int32m1_t
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vint32m1_t baz(vint32m1_t input);
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vint32m1_t test_no_vector_cc_attr(vint32m1_t input, int32_t *base, size_t vl) {
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vint32m1_t val = __riscv_vle32_v_i32m1(base, vl);
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vint32m1_t ret = baz(input);
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__riscv_vse32_v_i32m1(base, val, vl);
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return ret;
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}
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