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The Ampere1B is Ampere's third-generation core implementing a superscalar, out-of-order microarchitecture with nested virtualization, speculative side-channel mitigation and architectural support for defense against ROP/JOP style software attacks. Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all features of the second-generation Ampere1A, such as the Memory Tagging Extension and SM3/SM4 cryptography instructions.
19 lines
1.5 KiB
C
19 lines
1.5 KiB
C
// Test that target feature cssc is implemented and available correctly
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// FEAT_CSSC is a required part of v8.9a/v9.4a and optional from v8.7a/v9.3a onwards.
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf %s 2>&1 | FileCheck %s --check-prefix=ABSENT_CSSC
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv8.7-a+cssc %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv8.9-a %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv8.9-a+cssc %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv8.9-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.2-a+cssc %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+cssc %s 2>&1 | FileCheck %s
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -march=armv9.4-a+nocssc %s 2>&1 | FileCheck %s --check-prefix=NO_CSSC
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// RUN: %clang -S -o - -emit-llvm --target=aarch64-none-elf -mcpu=ampere1b %s 2>&1 | FileCheck %s
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// CHECK: "target-features"="{{.*}},+cssc
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// NO_CSSC: "target-features"="{{.*}},-cssc
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// ABSENT_CSSC-NOT: "target-features"="{{.*}},+cssc
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// ABSENT_CSSC-NOT: "target-features"="{{.*}},-cssc
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void test() {}
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