llvm-project/llvm/test/TableGen/SchedModelError.td
River Riddle 50d96f59d0 [TableGen] Track reference locations of Records/RecordVals
This is extremely useful for language tooling as it allows
for providing go-to-def/find-references/etc. for many
more situations than what is currently possible.

Differential Revision: https://reviews.llvm.org/D134087
2022-09-27 23:48:16 -07:00

19 lines
545 B
TableGen

// RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
include "llvm/Target/Target.td"
def TestTarget : Target;
// CHECK: [[FILE]]:[[@LINE+1]]:5: error: No schedule information for instruction 'TestInst' in SchedMachineModel 'TestSchedModel'
def TestInst : Instruction {
let OutOperandList = (outs);
let InOperandList = (ins);
bits<8> Inst = 0b00101010;
}
def TestSchedModel : SchedMachineModel {
let CompleteModel = 1;
}
def TestProcessor : ProcessorModel<"testprocessor", TestSchedModel, []>;