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llvm-project/llvm/lib/CodeGen/SelectionDAG
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Simon Pilgrim 1ba5c550d4 [DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x) 
Extend this to support ComputeNumSignBits of the (used) source vector elements so that we can handle more than just the case where we're sext_in_reg from the source element signbit.

Noticed while investigating the poor codegen in D98587.
2021-03-18 15:34:53 +00:00
..
CMakeLists.txt
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
DAGCombiner.cpp
[DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x)
2021-03-18 15:34:53 +00:00
FastISel.cpp
[FastISel] Don't trivially kill extractvalues (PR49467)
2021-03-09 18:46:38 +01:00
FunctionLoweringInfo.cpp
[NFC] Wisely nest dyn_cast in FunctionLoweringInfo
2021-03-16 10:22:44 +01:00
InstrEmitter.cpp
[DebugInfo] Emit DBG_VALUE_LIST from ISel
2021-03-09 12:17:39 +00:00
InstrEmitter.h
[DebugInfo] Emit DBG_VALUE_LIST from ISel
2021-03-09 12:17:39 +00:00
LegalizeDAG.cpp
[IR] Introduce llvm.experimental.vector.splice intrinsic
2021-03-09 10:44:22 +00:00
LegalizeFloatTypes.cpp
[Legalizer] Promote result type in expanding FP_TO_XINT
2021-01-18 11:56:11 +08:00
LegalizeIntegerTypes.cpp
[RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can represent a splat of 2 i32 values into a nxvXi64 vector for riscv32.
2021-03-10 09:46:18 -08:00
LegalizeTypes.cpp
[SelectionDAG] Use range-based for loops (NFC)
2021-02-09 22:14:30 -08:00
LegalizeTypes.h
[RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can represent a splat of 2 i32 values into a nxvXi64 vector for riscv32.
2021-03-10 09:46:18 -08:00
LegalizeTypesGeneric.cpp
[CodeGen] Refactor getMemBasePlusOffset & getObjectPtrOffset to accept a TypeSize
2020-08-11 12:17:10 +01:00
LegalizeVectorOps.cpp
[NFC] Unify FIME with FIXME in comments
2021-03-10 14:00:51 +01:00
LegalizeVectorTypes.cpp
[CodeGen] Fix issues with scalable-vector INSERT/EXTRACT_SUBVECTORs
2021-03-15 17:04:21 +00:00
ResourcePriorityQueue.cpp
…
ScheduleDAGFast.cpp
[DebugInstrRef] Create DBG_INSTR_REFs in SelectionDAG
2020-10-14 14:24:08 +01:00
ScheduleDAGRRList.cpp
Revert "[NFC][ScheduleDAG] Remove unused EntrySU SUnit"
2020-09-21 13:33:05 +02:00
ScheduleDAGSDNodes.cpp
[DebugInfo] Emit DBG_VALUE_LIST from ISel
2021-03-09 12:17:39 +00:00
ScheduleDAGSDNodes.h
…
ScheduleDAGVLIW.cpp
[SelectionDAG] Use range-based for loops (NFC)
2021-02-09 22:14:30 -08:00
SDNodeDbgValue.h
[DebugInfo] Handle dbg.values with multiple variable location operands in ISel
2021-03-09 09:48:03 +00:00
SelectionDAG.cpp
[DAG] SelectionDAG::isSplatValue - add ISD::ABS handling
2021-03-18 10:28:29 +00:00
SelectionDAGAddressAnalysis.cpp
[SelectionDAG] Avoid aliasing analysis if the object size is unknown.
2020-11-25 06:13:37 +08:00
SelectionDAGBuilder.cpp
Reapply "[DebugInfo] Handle multiple variable location operands in IR"
2021-03-17 16:45:25 +00:00
SelectionDAGBuilder.h
[IR] Introduce llvm.experimental.vector.splice intrinsic
2021-03-09 10:44:22 +00:00
SelectionDAGDumper.cpp
[RISCV][SelectionDAG] Introduce an ISD::SPLAT_VECTOR_PARTS node that can represent a splat of 2 i32 values into a nxvXi64 vector for riscv32.
2021-03-10 09:46:18 -08:00
SelectionDAGISel.cpp
[DebugInfo] Emit DBG_VALUE_LIST from ISel
2021-03-09 12:17:39 +00:00
SelectionDAGPrinter.cpp
[SelectionDAG] Drop unnecessary const from a return type (NFC)
2021-02-07 09:49:33 -08:00
SelectionDAGTargetInfo.cpp
…
StatepointLowering.cpp
[Statepoint Lowering] Handle the case with several gc.result
2021-03-11 18:44:44 +07:00
StatepointLowering.h
…
TargetLowering.cpp
[IR] Introduce llvm.experimental.vector.splice intrinsic
2021-03-09 10:44:22 +00:00